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"wu tsung yi"的相關文件
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| 國立臺灣體育運動大學 |
2011-03-01 |
急性健身運動對認知功能的影響事件相關電位的文獻回顧
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張育愷; 吳聰義; Chang, Yu-Kai; Wu, Tsung-Yi |
| 國立彰化師範大學 |
2010-12 |
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs
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Wu, Tsung-Yi; Kao, Tzi-Wei; Lin, How-Rern |
| 國立彰化師範大學 |
2010-08 |
Peak Current Reduction Using an MTCMOS Technique
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Lu, Liang-Ying; Wu, Tsung-Yi; Chiou, Lih-Yih; Shi, Jing-Wen |
| 國立彰化師範大學 |
2010-01 |
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC Designs
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Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 大葉大學 |
2009-05-25 |
A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm
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Wu, Tsung-Yi;Lin, How-Rern;Chen, Kuang-Yao;Huang, Shi-Yi;Li, Tai-Lun |
| 大葉大學 |
2009-05-25 |
A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers
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Wu, Tsung-Yi;Lin, How-Rern;Kao, Tzi-Wei;Huang, Shi-Yi;Li, Tai-Lun |
| 國立彰化師範大學 |
2009-05 |
A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm
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Wu, Tsung-Yi; Chen, Kuang-Yao; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 國立彰化師範大學 |
2009-05 |
A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers
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Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern |
| 大葉大學 |
2009-04-1 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
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Lin, How-Rern;Chiu, Wei-Hao;Wu, Tsung-Yi |
| 大葉大學 |
2009-04-01 |
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
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Lin, How-Rern;Chiu, Wei-Hao;Wu, Tsung-Yi |
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