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Showing items 81-130 of 348 (7 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T15:23:14Z	Nanowire-aware routing considering high cut mask complexity	Su, Y.-H.;Chang, Y.-W.; Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T15:23:14Z	Layout-dependent-effects-aware analytical analog placement	Ou, H.-C.;Tseng, K.-H.;Liu, J.-Y.;Wu, I.-P.;Chang, Y.-W.; Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T15:23:14Z	Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning	Fang, S.-Y.;Tai, Y.-S.;Chang, Y.-W.; Fang, S.-Y.; Tai, Y.-S.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T15:00:43Z	Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification	Chi-Yuan Liu;Hui-Ju K. Chiang;Yao-Wen Chang;Jie-Hong R. Jiang; Chi-Yuan Liu; Hui-Ju K. Chiang; Yao-Wen Chang; Jie-Hong R. Jiang; YAO-WEN CHANG; JIE-HONG JIANG
臺大學術典藏	2018-09-10T14:59:36Z	Theory of charge transport in molecular junctions: From Coulomb blockade to coherent tunneling	Yao-Wen Chang; Bih-Yaw Jin; BIH-YAW JIN
臺大學術典藏	2018-09-10T14:58:00Z	A new asynchronous pipeline template for power and performance optimization	Ho, K.-H.;Chang, Y.-W.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	Simultaneous EUV flare- and CMP-aware placement	Liu, C.-Y.;Chang, Y.-W.; Liu, C.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	Routability-driven blockage-aware macro placement	Chen, Y.-F.;Huang, C.-C.;Chiou, C.-H.;Chang, Y.-W.;Wang, C.-J.; Chen, Y.-F.; Huang, C.-C.; Chiou, C.-H.; Chang, Y.-W.; Wang, C.-J.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	Overlay-Aware detailed routing for self-Aligned double patterning lithography using the cut process	Liu, I.-J.;Fang, S.-Y.;Chang, Y.-W.; Liu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	Obstacle-avoiding free-assignment routing for flip-chip designs	YAO-WEN CHANG; Ho, Y.-K.;Lee, H.-C.;Lee, W.;Chang, Y.-W.;Chang, C.-F.;Lin, I.-J.;Shen, C.-F.; Ho, Y.-K.; Lee, H.-C.; Lee, W.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.
臺大學術典藏	2018-09-10T14:57:59Z	NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs	Hsu, M.-K.;Chen, Y.-F.;Huang, C.-C.;Chou, S.;Lin, T.-H.;Chen, T.-C.;Chang, Y.-W.; Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chou, S.; Lin, T.-H.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	Nonuniform multilevel analog routing with matching constraints	Ou, H.-C.;Chien, H.-C.C.;Chang, Y.-W.; Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	Functional ECO using metal-configurable gate-array spare cells	Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	Buffered clock tree synthesis considering self-heating effects	Lin, C.-W.;Hsu, T.-H.;Shih, X.-W.;Chang, Y.-W.; Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T14:57:59Z	A novel layout decomposition algorithm for triple patterning lithography	Fang, S.-Y.;Chang, Y.-W.;Chen, W.-Y.; Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:08Z	Escape routing for staggered-pin-array PCBs	Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG; Ho, Y.-K.; Ho, Y.-K.;Lee, H.-C.;Chang, Y.-W.
臺大學術典藏	2018-09-10T09:48:08Z	ECO optimization using metal-configurable gate-array spare cells	Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:08Z	Double patterning lithography-aware analog placement	Chien, H.-C.C.;Ou, H.-C.;Chen, T.-C.;Kuan, T.-Y.;Chang, Y.-W.; Chien, H.-C.C.; Ou, H.-C.; Chen, T.-C.; Kuan, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:08Z	Coupling-Aware length-ratio-matching routing for capacitor arrays in analog integrated circuits	Ho, K.-H.;Ou, H.-C.;Chang, Y.-W.;Tsao, H.-F.; Ho, K.-H.; Ou, H.-C.; Chang, Y.-W.; Tsao, H.-F.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:08Z	An efficient and effective analytical placer for FPGAs	YAO-WEN CHANG; Chang, Y.-W.; Banerjee, P.; Lin, T.-H.; Lin, T.-H.;Banerjee, P.;Chang, Y.-W.
臺大學術典藏	2018-09-10T09:48:07Z	Stitch-aware routing for multiple e-beam lithography	Fang, S.-Y.;Liu, I.-J.;Chang, Y.-W.; Fang, S.-Y.; Liu, I.-J.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Layer minimization in escape routing for staggered-pin-array PCBs	Ho, Y.-K.;Shih, X.-W.;Chang, Y.-W.;Cheng, C.-K.; Ho, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model	Hsu, M.-K.;Balabanov, V.;Chang, Y.-W.; Hsu, M.-K.; Balabanov, V.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Technical perspective: Circuit placement challenges	Chang, Y.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Symmetrical buffered clock-tree synthesis with supply-voltage alignment	Shih, X.-W.;Hsu, T.-H.;Lee, H.-C.;Chang, Y.-W.;Chao, K.-Y.; Shih, X.-W.; Hsu, T.-H.; Lee, H.-C.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling	Fang, S.-Y.;Lin, C.-W.;Liao, G.-W.;Chang, Y.-W.; Fang, S.-Y.; Lin, C.-W.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Simultaneous analog placement and routing with current flow and current density considerations	Ou, H.-C.;Chien, H.-C.C.;Chang, Y.-W.; Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Routability-driven placement for hierarchical mixed-size circuit designs	Hsu, M.-K.;Chen, Y.-F.;Huang, C.-C.;Chen, T.-C.;Chang, Y.-W.; Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Multiple chip planning for chip-interposer codesign	Ho, Y.-K.;Chang, Y.-W.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:48:07Z	Graph-based subfield scheduling for electron-beam photomask fabrication	Fang, S.-Y.;Chen, W.-Y.;Chang, Y.-W.; Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:24:00Z	Correlation effects of π electrons on the band structures of conjugated polymers using the self-consistent GW approximation with vertex corrections	Yao-Wen Chang; Bih-Yaw Jin; Yao-Wen Chang; Bih-Yaw Jin; BIH-YAW JIN
臺大學術典藏	2018-09-10T09:22:26Z	Non-uniform multilevel analog routing with matching constraints	Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:26Z	Native-conflict and stitch-aware wire perturbation for double patterning technology	Fang, S.-Y.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:26Z	Graph-based subfield scheduling for electron-beam photomask fabrication	Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:26Z	Fast timing-model independent buffered clock-tree synthesis	Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:26Z	An efficient Pre-assignment routing algorithm for flip-chip designs	Lin, C.-W.; Lee, P.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:26Z	A novel layout decomposition algorithm for triple patterning lithography	Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:26Z	A chip-package-board co-design methodology	Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:25Z	Unified analytical global placement for large-scale mixed-size circuit designs	Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:25Z	TRECO: Dynamic technology remapping for timing engineering change orders	Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG; JIE-HONG JIANG
臺大學術典藏	2018-09-10T09:22:25Z	Timing ECO optimization via B?zier curve smoothing and fixability identification	Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:25Z	Timing ECO optimization using metal-configurable gate-array spare cells	Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:25Z	Structure-aware placement for datapath-intensive circuit designs	Chou, S.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:25Z	Simultaneous flare level and flare variation minimization with dummification in EUVL	Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T09:22:25Z	Obstacle-avoiding free-assignment routing for flip-chip designs	Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:42:39Z	A corner stitching compliant B-tree representation and its applications to analog placement	YAO-WEN CHANG; Tsao, H.-F.;Chou, P.-Y.;Huang, S.-L.;Chang, Y.-W.;Lin, M.P.-H.;Chen, D.-P.;Liu, D.; Tsao, H.-F.; Chou, P.-Y.; Huang, S.-L.; Chang, Y.-W.; Lin, M.P.-H.; Chen, D.-P.; Liu, D.
臺大學術典藏	2018-09-10T08:42:38Z	Hierarchical placement with layout constraints	Lin, M.P.-H.;Chang, Y.-W.; Lin, M.P.-H.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:42:38Z	Heterogeneous B*-trees for analog placement with symmetry and regularity considerations	Chou, P.-Y.;Ou, H.-C.;Chang, Y.-W.; Chou, P.-Y.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:42:38Z	Escape routing for staggered-pin-array PCBs	Ho, Y.-K.;Lee, H.-C.;Chang, Y.-W.; Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:42:38Z	Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips	Lin, C.C.-Y.;Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG

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