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"yao wen chang"的相关文件
显示项目 81-105 / 348 (共14页)
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| 臺大學術典藏 |
2018-09-10T15:23:14Z |
Nanowire-aware routing considering high cut mask complexity
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Su, Y.-H.;Chang, Y.-W.; Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T15:23:14Z |
Layout-dependent-effects-aware analytical analog placement
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Ou, H.-C.;Tseng, K.-H.;Liu, J.-Y.;Wu, I.-P.;Chang, Y.-W.; Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T15:23:14Z |
Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning
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Fang, S.-Y.;Tai, Y.-S.;Chang, Y.-W.; Fang, S.-Y.; Tai, Y.-S.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T15:00:43Z |
Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification
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Chi-Yuan Liu;Hui-Ju K. Chiang;Yao-Wen Chang;Jie-Hong R. Jiang; Chi-Yuan Liu; Hui-Ju K. Chiang; Yao-Wen Chang; Jie-Hong R. Jiang; YAO-WEN CHANG; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T14:59:36Z |
Theory of charge transport in molecular junctions: From Coulomb blockade to coherent tunneling
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Yao-Wen Chang; Bih-Yaw Jin; BIH-YAW JIN |
| 臺大學術典藏 |
2018-09-10T14:58:00Z |
A new asynchronous pipeline template for power and performance optimization
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Ho, K.-H.;Chang, Y.-W.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Simultaneous EUV flare- and CMP-aware placement
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Liu, C.-Y.;Chang, Y.-W.; Liu, C.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Routability-driven blockage-aware macro placement
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Chen, Y.-F.;Huang, C.-C.;Chiou, C.-H.;Chang, Y.-W.;Wang, C.-J.; Chen, Y.-F.; Huang, C.-C.; Chiou, C.-H.; Chang, Y.-W.; Wang, C.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Overlay-Aware detailed routing for self-Aligned double patterning lithography using the cut process
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Liu, I.-J.;Fang, S.-Y.;Chang, Y.-W.; Liu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Obstacle-avoiding free-assignment routing for flip-chip designs
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YAO-WEN CHANG; Ho, Y.-K.;Lee, H.-C.;Lee, W.;Chang, Y.-W.;Chang, C.-F.;Lin, I.-J.;Shen, C.-F.; Ho, Y.-K.; Lee, H.-C.; Lee, W.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F. |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs
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Hsu, M.-K.;Chen, Y.-F.;Huang, C.-C.;Chou, S.;Lin, T.-H.;Chen, T.-C.;Chang, Y.-W.; Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chou, S.; Lin, T.-H.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Nonuniform multilevel analog routing with matching constraints
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Ou, H.-C.;Chien, H.-C.C.;Chang, Y.-W.; Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Functional ECO using metal-configurable gate-array spare cells
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Buffered clock tree synthesis considering self-heating effects
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Lin, C.-W.;Hsu, T.-H.;Shih, X.-W.;Chang, Y.-W.; Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
A novel layout decomposition algorithm for triple patterning lithography
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Fang, S.-Y.;Chang, Y.-W.;Chen, W.-Y.; Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:08Z |
Escape routing for staggered-pin-array PCBs
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Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG; Ho, Y.-K.; Ho, Y.-K.;Lee, H.-C.;Chang, Y.-W. |
| 臺大學術典藏 |
2018-09-10T09:48:08Z |
ECO optimization using metal-configurable gate-array spare cells
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:08Z |
Double patterning lithography-aware analog placement
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Chien, H.-C.C.;Ou, H.-C.;Chen, T.-C.;Kuan, T.-Y.;Chang, Y.-W.; Chien, H.-C.C.; Ou, H.-C.; Chen, T.-C.; Kuan, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:08Z |
Coupling-Aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
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Ho, K.-H.;Ou, H.-C.;Chang, Y.-W.;Tsao, H.-F.; Ho, K.-H.; Ou, H.-C.; Chang, Y.-W.; Tsao, H.-F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:08Z |
An efficient and effective analytical placer for FPGAs
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YAO-WEN CHANG; Chang, Y.-W.; Banerjee, P.; Lin, T.-H.; Lin, T.-H.;Banerjee, P.;Chang, Y.-W. |
| 臺大學術典藏 |
2018-09-10T09:48:07Z |
Stitch-aware routing for multiple e-beam lithography
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Fang, S.-Y.;Liu, I.-J.;Chang, Y.-W.; Fang, S.-Y.; Liu, I.-J.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:07Z |
Layer minimization in escape routing for staggered-pin-array PCBs
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Ho, Y.-K.;Shih, X.-W.;Chang, Y.-W.;Cheng, C.-K.; Ho, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:07Z |
TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model
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Hsu, M.-K.;Balabanov, V.;Chang, Y.-W.; Hsu, M.-K.; Balabanov, V.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:07Z |
Technical perspective: Circuit placement challenges
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Chang, Y.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:07Z |
Symmetrical buffered clock-tree synthesis with supply-voltage alignment
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Shih, X.-W.;Hsu, T.-H.;Lee, H.-C.;Chang, Y.-W.;Chao, K.-Y.; Shih, X.-W.; Hsu, T.-H.; Lee, H.-C.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG |
显示项目 81-105 / 348 (共14页)
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每页显示[10|25|50]项目
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