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"yao wen chang"的相關文件
顯示項目 286-295 / 348 (共35頁)
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| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Placement with alignment and performance constraints using the B*-tree representation
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Wu, M.-C.; Chang, Y.-W.; Wu, M.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Multilevel routing with jumper insertion for antenna avoidance
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Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Multilevel routing with antenna avoidance
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Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Layout techniques for on-chip interconnect inductance reduction
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Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
Switch module design with application to two-dimensional segmentation design
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Zhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
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Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.T.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Rectilinear block placement using B*-trees
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Wu, G.-M.; Chang, Y.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Noise-aware buffer planning for interconnect-driven floorplanning
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Li, S.-M.; Cherng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Multilevel floorplanning/placement for large-scale modules using B*-trees
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YAO-WEN CHANG; Yang, H.H.; Hsu, J.-M.; Chang, Y.-W.; Lee, H.-C. |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Graph matching-based algorithms for array-based FPGA segmentation design and routing
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Lin, J.-M.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG |
顯示項目 286-295 / 348 (共35頁)
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