| 臺大學術典藏 |
2018-09-10T07:43:05Z |
An experimental ultra-low-voltage demodulator in 0.18 µm CMOS
|
L.-S. Lai;H.-H. Hsieh;P.-S. Weng;L.-H. Lu; L.-S. Lai; H.-H. Hsieh; P.-S. Weng; L.-H. Lu; LIANG-HUNG LU |
| 臺大學術典藏 |
2018-09-10T07:43:05Z |
Small- and large-signal operation of X-band CE and CB SiGe/Si power HBT’s
|
J.-S. Rieh; L.-H. Lu; Z. Ma; X. Liu; P. B. K. Katehi; P. Bhattacharya; E. T. Croke; LIANG-HUNG LU |
| 臺大學術典藏 |
2018-09-10T07:43:05Z |
A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation
|
K-J Hsian;Tai-Cheng Lee; K-J Hsian; Tai-Cheng Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T07:43:06Z |
Time-space test response compaction and diagnosis based on BCH codes
|
F. M. Wang;W.-C. Wang;J. C-M. Li; F. M. Wang; W.-C. Wang; J. C-M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:06Z |
Transition Fault Diagnosis Using At-speed Test Patterns
|
Shang-Feng Chao;Jheng-Yang Ciou;James Chien-Mo Li; Shang-Feng Chao; Jheng-Yang Ciou; James Chien-Mo Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:06Z |
Bridging Fault Diagnosis to Identify the Layer of Systematic Defects
|
B. R. Chen;J. C.M. Li; B. R. Chen; J. C.M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:07Z |
Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits
|
Shiue-Tsung Shen,;Wei-Hsiao Liu,;En-Hua Ma,;J. C.-M. Li,;I-Chun Cheng,; Shiue-Tsung Shen,; Wei-Hsiao Liu,; En-Hua Ma,; J. C.-M. Li,; I-Chun Cheng,; I-CHUN CHENG; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:07Z |
Power Scan: DFT for Power Switches in VLSI Designs
|
B. C. Bai; B. C. Bai; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
|
B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
BIST Design Optimization for Large-Scale Embedded Memory Cores
|
T.-F. Chien;W.-C. Chao;J. C.-M. Li;K.-Y. Liao;Y.-W. Chang;M.-T. Chang;M.-H. Tsai;C.-M. Tseng; T.-F. Chien; W.-C. Chao; J. C.-M. Li; K.-Y. Liao; Y.-W. Chang; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Electronic Design Automation
|
J. C.-M. Li;M. Hsiao; J. C.-M. Li; M. Hsiao; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
包含未知訊號之測試結果壓縮設計
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王偉哲;李建模; 王偉哲 李建模; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation
|
Chung-Ping Chen; Chris C. N. Chu; D. F. Wong; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Noise-Aware Repeater Insertion and Wire-Sizing for On-chip Interconnect Using Hierarchical Moment-Matching
|
Chung-Ping Chen; N. Menezes; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Error-bounded Pade Approximation via Bilinear Conformal Transformation
|
Chung-Ping Chen; D.F. Wong; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
Spec-based Repeater Insertion and Wire-Sizing for On-chip Interconnect
|
N. Menezes; Chung-Ping Chen; CHUNG-PING CHEN |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs
|
T.-H. Lin;C.-L. Ti;Y.-H. Liu; T.-H. Lin; C.-L. Ti; Y.-H. Liu; Lin, Tsung-Hsien |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
A 200-pJ/b MUX-based RF Transmitter for Implantable Multi-Channel Neural Recording
|
Y.-H. Liu;C.-L. Li;T.-H. Lin; Y.-H. Liu; C.-L. Li; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
Wireless Integrated Network Sensors (WINS)
|
TSUNG-HSIEN LIN; G. Asada; I. Bhatti; T.-H. Lin; S. Natkunanthanan; F. Newberg; R. Rofougaran; A. Sipos; S. Valoff; G. J. Pottie; W. J. Kaiser |
| 臺大學術典藏 |
2018-09-10T07:43:09Z |
A Low-Power VLSI Neural Processor Design for Image Data Compression in a SOI CMOS Technology
|
W. Fang; E. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A Super-Regenerative ASK Receiver with Delta-Sigma Pulse-width Digitizer and SAR-based Fast Frequency Calibration for MICS Applications
|
Y.-H. Liu;H.-H. Liu;T.-H. Lin; Y.-H. Liu; H.-H. Liu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A 5GHz Phase-Locked Loop Using Dynamic Phase-Error Compensation Technique for Fast Settling in 0.18-μm CMOS
|
W.-H. Chiu;Y.-H. Huang;T.-H. Lin; W.-H. Chiu; Y.-H. Huang; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A Time-Domain-Based Self-Calibrated Analog-to-Digital Converter With A Linear Voltage-to-Delay Circuit in 0.18-μm CMOS
|
C.-H. Yang;W.-H. Chiu;T.-H. Lin; C.-H. Yang; W.-H. Chiu; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
A charge pump current missmatch calibration technique for ΔΣ fractional-N PLLs in 0.18-μm CMOS
|
W.-H. Chiu;T.-S. Chang;T.-H. Lin; W.-H. Chiu; T.-S. Chang; T.-H. Lin; TSUNG-HSIEN LIN |
| 臺大學術典藏 |
2018-09-10T07:43:10Z |
Delta sigma modulator and method for compensating delta sigma modulators for loop delay
|
Chan-Hsiang Weng;Tsung-Hsien Lin; Chan-Hsiang Weng; Tsung-Hsien Lin; TSUNG-HSIEN LIN |
