English  |  正體中文  |  简体中文  |  总笔数 :2853327  
造访人次 :  45102119    在线人数 :  847
教育部委托研究计画      计画执行:国立台湾大学图书馆
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
关于TAIR

浏览

消息

著作权

相关连结

跳至:
或输入年份:
从最近的开始 由旧到新排序

显示项目 1978276-1978285 / 2346269 (共234627页)
<< < 197823 197824 197825 197826 197827 197828 197829 197830 197831 197832 > >>
每页显示[10|25|50]项目

机构 日期 题名 作者
臺大學術典藏 2018-09-10T06:03:12Z Method and Apparatus for Feedback Error Detection in a Wireless Communications System A. Das; F. Khan; A. Sampath; H.-J. Su; HSUAN-JUNG SU
臺大學術典藏 2018-09-10T06:03:13Z Performance Analysis of Bit-Interleaved Space-Time (BI-ST) Coded Systems over Wireless Channels S. Zummo; P.C. Yeh; W. Stark; PING-CHENG YEH
臺大學術典藏 2018-09-10T06:03:13Z A low-cost jitter measurement technique for BIST applications Huang, Jiun-Lang; J.-L. Huang; J.-J. Huang; Y.-S. Liu
臺大學術典藏 2018-09-10T06:03:13Z On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏 2018-09-10T06:03:14Z A routability constrained scan chain ordering technique for test power reduction X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏 2018-09-10T06:03:14Z A period tracking based on-chip sinusoidal jitter extraction technique C.-Y. Kuo; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏 2018-09-10T06:03:14Z An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing S.-W. Chang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏 2018-09-10T06:03:14Z A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏 2018-09-10T06:03:15Z A low-power oscillator mixer in 0.18-um CMOS technology LIANG-HUNG LU; H. Wang; T.-P. Wang; C.-C. Chang; R.-C. Liu; M.-D. Tsai; K.-J. Sun; Y.-T. Chang; L.-H. Lu
臺大學術典藏 2018-09-10T06:03:15Z A wide-tuning-range CMOS VCO with a differential tunable active inductor L.-H. Lu; H.-H. Hsieh; Y.-T. Liao; LIANG-HUNG LU

显示项目 1978276-1978285 / 2346269 (共234627页)
<< < 197823 197824 197825 197826 197827 197828 197829 197830 197831 197832 > >>
每页显示[10|25|50]项目