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Showing items 6-30 of 70  (3 Page(s) Totally)
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Institution Date Title Author
國立臺灣科技大學 2019 Resistive open defect detection in SoCs by a test method based on injected charge volume after test input application Matsumoto, Y.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2019 Stand-by mode test method of interconnects between dies in 3d ICs with IEEE 1149.1 test circuits Kanda, M.;Yabui, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2019 Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM Lu, S.-K.;Huang, Huang H.-K.;Hsu, C.-L.;Sun, C.-T.;Miyase, K.
國立臺灣科技大學 2019 A fault-tolerant MPSoC for CubeSats Fuchs, C.M.;Chou, P.;Wen, X.;Murillo, N.M.;Furano, G.;Holst, S.;Tavoularis, A.;Lu, S.-K.;Plaat, A.;Marinis, K.
國立臺灣科技大學 2019 A static method for analyzing hotspot distribution on the LSI Miyase, K.;Kawano, Y.;Lu, S.-K.;Wen, X.;Kajihara, S.
國立臺灣科技大學 2018 A design for testability of open defects at interconnects in 3D stacked ICs Ashikin F.; Hashizume M.; Yotsuyanagi H.; Lu S.-K.; Roth Z.
國立臺灣科技大學 2018 Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories Lu S.-K.; Jheng H.-C.; Lin H.-W.; Hashizume M.
國立臺灣科技大學 2018 Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories Lu S.-K.; Zhong S.-X.; Hashizume M.
國立臺灣科技大學 2018 A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2018 A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2018 Open defect detection with a built-in test circuit by IDDT appearance time in CMOS ICs Kambara A.; Yotsuyanagi H.; Miyoshi D.; Hashizume M.; Lu S.-K.
國立臺灣科技大學 2018 Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory Lu S.-K.; Li H.-P.; Miyase K.
國立臺灣科技大學 2018 Fault-aware page address remapping techniques for enhancing yield and reliability of flash memories Lu S.-K.; Yu S.-C.; Hashizume M.; Yotsuyanagi H.
國立臺灣科技大學 2018 Progressive ECC Techniques for Phase Change Memory Lu, S.-K.;Li, H.-P.;Miyase, K.
國立臺灣科技大學 2017 Online slack-Time binning for IO-registered die-To-die interconnects Zheng, C.-C;Huang, S.-Y;Lu, S.-K;Wang, T.-C;Tsai, K.-H;Cheng, W.-T.
國立臺灣科技大學 2017 Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power Lu, S.-K.;Huang, Huang H.-K.
國立臺灣科技大學 2017 Electrical tests for capacitive open defects in assembled PCBs Alia, F.A.B.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2017 Electrical test of resistive and capacitive open defects at data bus in 3D memory IC Hashizume, M.;Shiraishi, Y.;Yotsuyanagi, H.;Yokoyama, H.;Tada, Tada T.;Lu, S.-K.
國立臺灣科技大學 2017 Resistive open defects detected by interconnect testing based on charge volume injected to 3D ICs Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2017 A built-in current sensor made of a comparator of offset cancellation type for electrical interconnect tests of 3D ICs Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2016 A Framework for Third Party Android Marketplaces to Identify Repackaged Apps Lo, N.-W;Lu, S.-K;Chuang, Y.-H.
國立臺灣科技大學 2016 Integrated heterogeneous infrastructure for indoor positioning Ma, Y.-W;Chen, J.-L;Tsai, Y.-H;Chou, P.-C;Lu, S.-K;Kuo, S.-Y.
國立臺灣科技大學 2016 Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories Lu, S.-K;Tsai, C.-J;Hashizume, M.
國立臺灣科技大學 2016 A built-in electrical test circuit for detecting open leads in assembled PCB circuits Miyabe, T;Hashizume, M;Yotsuyanagi, H;Lu, S.-K;Roth, Z.
國立臺灣科技大學 2016 Electrical interconnect test of solder joint part with boundary scan flip flops and a built-in test circuit Hashizume, M;Ikiri, Y;Konishi, T;Yotsuyanagi, H;Lu, S.-K.

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