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Institution	Date	Title	Author
國立交通大學	2014-12-08T15:11:24Z	ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers	Ker, Ming-Dou; Chang, Wei-Jen
國立交通大學	2017-04-21T06:55:35Z	ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC	Dai, Chia-Tsen; Ker, Ming-Dou
國立交通大學	2017-04-21T06:50:10Z	ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC	Dai, Chia-Tsen; Ker, Ming-Dou
國立交通大學	2014-12-08T15:26:55Z	ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design	Chen, TY; Ker, MD
國立交通大學	2014-12-16T06:15:12Z	ESD PROTECTION STRUCTURE FOR 3D IC	Chen Kuan-Neng; Lai Ming-Fang; Chen Hung-Ming
國立交通大學	2014-12-08T15:25:32Z	ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications	Ker, MD; Chang, WJ; Yang, M; Chen, CC; Chan, MC; Shieh, WT; Yen, KL
國立交通大學	2014-12-08T15:28:05Z	ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process	Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Chang, Tzu-Heng
國立交通大學	2014-12-08T15:43:41Z	ESD protection under grounded-up bond pads in 0.13 mu m eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology	Chou, KY; Chen, MJ
大葉大學	2000	ESD robustness designs of power MOSFET ICs	陳勝利
大葉大學	2000-11	ESD Robustness Designs of Power MOSFET ICs	陳勝利

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