| 國立臺灣科技大學 |
2009-09 |
A 0.22 V Quadrature VCO in 90 nm CMOS Process
|
Sheng-Lyang Jang;Chuang-Jen Huang;Cheng-Chen Liu;Ching-Wen Hsue |
| 國立交通大學 |
2014-12-08T15:08:26Z |
A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
|
Wong, Cheng-Chi; Tang, Cheng-Hao; Lai, Ming-Wei; Zheng, Yan-Xiu; Lin, Chien-Ching; Chang, Hsie-Chia; Lee, Chen-Yi; Su, Yu-T. |
| 國立成功大學 |
2003-02 |
A 0.25-mu m 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer
|
Yen, Cheng-Chi; Chuang, Huey-Ru |
| 臺大學術典藏 |
2018-09-10T09:25:34Z |
A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression
|
T.-T. Liu;J. Rabaey; T.-T. Liu; J. Rabaey; TSUNG-TE LIU |
| 臺大學術典藏 |
2018-09-10T09:50:56Z |
A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression
|
Liu, T.-T.;Rabaey, J.M.; Liu, T.-T.; Rabaey, J.M.; TSUNG-TE LIU |
| 臺大學術典藏 |
2019-10-31T07:12:33Z |
A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting
|
HSIN-SHU CHEN;Wen-Jong Wu;Micka?l Lallart;Hsin-Shu Chen;Kai-Ren Cheng; Kai-Ren Cheng; Hsin-Shu Chen; Micka?l Lallart; Wen-Jong Wu; HSIN-SHU CHEN |
| 臺大學術典藏 |
2020-01-17T07:48:26Z |
A 0.25�gm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting
|
WEN-JONG WU;Wu, W.-J.;Lallart, M.;Chen, H.-S.;Cheng, K.-R.; Cheng, K.-R.; Chen, H.-S.; Lallart, M.; Wu, W.-J.; WEN-JONG WU |
| 國立臺灣科技大學 |
2010-03 |
A 0.3 V Cross-Coupled VCO Using Dynamic Threshold MOSFET
|
Sheng-Lyang Jang;Chuang-Jen Huang;Ching-Wen Hsue;Chia-Wei Chang |
| 朝陽科技大學 |
2021-10-02 |
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications
|
Lin,Jin-Fa; Tsai, Chang-Ming; Tsai, Ming-Yan; Hsia, Shih-Chang; Morsalin, S. M. Salahuddin; Sheu, Ming-Hwa; 林進發 |
| 國立臺灣大學 |
2004 |
A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-μm CMOS technology
|
Tsai, Ming-Da; Wang, Huei |
| 臺大學術典藏 |
2020-06-11T06:16:48Z |
A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillator
|
Chang, C.-K.;Tsai, Y.-K.;Cheng, K.-H.;Lu, L.-H.; Chang, C.-K.; Tsai, Y.-K.; Cheng, K.-H.; Lu, L.-H.; LIANG-HUNG LU |
| 國立交通大學 |
2015-07-21T08:29:40Z |
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
|
Lu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Ya-Ping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin |
| 臺大學術典藏 |
2020-06-11T06:31:42Z |
A 0.33 V 683 μW K-band transformer-based receiver front-end in 65 nm CMOS technology
|
Cheng, J.-H.;Hsieh, C.-L.;Wu, M.-H.;Tsai, J.-H.;Huang, T.-W.; Cheng, J.-H.; Hsieh, C.-L.; Wu, M.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
|
Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立臺灣科技大學 |
2010 |
A 0.35 mu m CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage-current feedback topology
|
Jang, S.L.;Liu, C.C.;Yang, R.K.;Shih, C.C.;Chang, C.W.;Yeh, H.A. |
| 國立交通大學 |
2017-04-21T06:55:34Z |
A 0.35 V, 375 kHz, 5.43 mu W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
|
Wu, Shang-Lin; Lu, Chien-Yu; Tu, Ming-Hsien; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te |
| 國立臺灣科技大學 |
2011 |
A 0.35-mu m CMOS CROSS-COUPLED COMPLEMENTARY COLPITTS VOLTAGE CONTROLLED OSCILLATOR
|
Jang, S.L.;Liu, W.C.;Chang, C.W.;Huang, J.F. |
| 國立臺灣科技大學 |
2010 |
A 0.35-mu m CMOS DIVIDE-BY-3 LC INJECTION-LOCKED FREQUENCY DIVIDER USING LINEAR MIXERS
|
Jang, S.L.;Chen, H.S.;Liu, C.C.;Juang, M.H. |
| 國立臺灣科技大學 |
2011 |
A 0.35-mu m CMOS FREQUENCY DIVIDER IMPLEMENTED WITH THE WAFFLE INJECTION MOSFET
|
Jang, S.L.;Cheng, C.L.;Chang, C.W.;Juang, M.H. |
| 國立臺灣科技大學 |
2008-04 |
A 0.35-um CMOS switched-inductor dual-band LC-tank frequency divider
|
Sheng-Lyang Jang;Che Yi Lin;Chien-Feng Lee |
| 國立臺灣科技大學 |
2008 |
A 0.35-um CMOS switched-inductor dual-band LC-tank frequency divider
|
Jang S.-L.; Che Y.L.; Lee C.-F. |
| 國立交通大學 |
2020-02-02T23:54:35Z |
A 0.35-V 240-W Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications
|
Wang, Shih-Hsing; Hung, Chung-Chih |
| 國立臺灣科技大學 |
2009-04 |
A 0.35?m CMOS divide-by-3 LC injection-locked frequency divider
|
Sheng-Lyang Jang;Chuang-Jen Huang;Cheng-Chen Liu |
| 元智大學 |
2016-08-02 |
A 0.35V, 500Mbps Digitalized LVDS driver in 0.18m CMOS technology
|
Shi-Fung Zhou; Hungwen Lin |
| 國立臺灣科技大學 |
2009 |
A 0.35弮m CMOS divide-by-3 LC injection-locked frequency divider
|
Jang S.-L.; Huang C.-J.; Liu C.-C. |
