| 臺大學術典藏 |
2018-09-10T09:25:23Z |
A 0.18 um CMOS self-mixing frequency tripler
|
Y.-T. Lo;J.-F. Kiang; Y.-T. Lo; J.-F. Kiang; JEAN-FU KIANG |
| 國立中山大學 |
2006-04 |
A 0.18 µm CMOS prototype of COFDM demodulator for European DVB-T standard
|
C.C. Wang;J.M. Huang;Y.M. Tseng;C.Y. Chang |
| 國立交通大學 |
2014-12-08T15:19:20Z |
A 0.18-mu m CMOS CMFB downconversion micromixer with deep N-well technology for LO-RF and LO-IF isolation improvements
|
Meng, CC; Hsu, SK; Wu, TH; Huang, GW |
| 臺大學術典藏 |
2018-09-10T09:43:53Z |
A 0.18-μ m CMOS Dual-band frequency synthesizer with spur reduction calibration
|
Chen, Y.-W.;Yu, Y.-H.;Chen, Y.-J.E.; Chen, Y.-W.; Yu, Y.-H.; Chen, Y.-J.E.; YI-JAN EMERY CHEN |
| 國立臺灣大學 |
2008 |
A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier
|
Wang, I-Hsin; Liu, Shen-Iuan |
| 臺大學術典藏 |
2018-09-10T08:14:43Z |
A 0.18-μm CMOS RF transceiver with self-detection and calibration functions for bluetooth V2.1 + EDR applications
|
Hu, W.-Y.;Lin, J.-W.;Tien, K.-C.;Hsieh, Y.-H.;Chen, C.-L.;Tso, H.-T.;Shih, Y.-S.;Hu, S.-C.;Chen, S.-J.; Hu, W.-Y.; Lin, J.-W.; Tien, K.-C.; Hsieh, Y.-H.; Chen, C.-L.; Tso, H.-T.; Shih, Y.-S.; Hu, S.-C.; Chen, S.-J.; SAO-JIE CHEN |
| 國立高雄師範大學 |
2006-08 |
A 0.18-μm CMOS UWB Low Noise Amplifier for 3.1-7.4GHz
|
Ruey-Lue Wang;Hsiang-Chen Kuo;Shih-Chih Chen; 王瑞祿 |
| 國立高雄師範大學 |
2006-12 |
A 0.18-μm CMOS UWB Low Noise Amplifier for Full-Band(3.1-10.6GHZ) Application
|
Ruey-Lue Wang;Shih-Chih Chen;Hsiang-Chen Kuo;Chien-Hsuan Liu; 王瑞祿 |
| 國立臺灣科技大學 |
2012 |
A 0.18-μm SiGe BiCMOS HBT VCO using diode degeneration
|
Jang, S.-L.;Hsieh, C.-W.;Chang, C.-W.;Hsue, C.-W. |
| 國立交通大學 |
2019-04-02T06:04:26Z |
A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications
|
Hong, Hao-Chiao; Chiu, Yi |
| 國立臺灣科技大學 |
2009-09 |
A 0.22 V Quadrature VCO in 90 nm CMOS Process
|
Sheng-Lyang Jang;Chuang-Jen Huang;Cheng-Chen Liu;Ching-Wen Hsue |
| 國立交通大學 |
2014-12-08T15:08:26Z |
A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
|
Wong, Cheng-Chi; Tang, Cheng-Hao; Lai, Ming-Wei; Zheng, Yan-Xiu; Lin, Chien-Ching; Chang, Hsie-Chia; Lee, Chen-Yi; Su, Yu-T. |
| 國立成功大學 |
2003-02 |
A 0.25-mu m 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer
|
Yen, Cheng-Chi; Chuang, Huey-Ru |
| 臺大學術典藏 |
2018-09-10T09:25:34Z |
A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression
|
T.-T. Liu;J. Rabaey; T.-T. Liu; J. Rabaey; TSUNG-TE LIU |
| 臺大學術典藏 |
2018-09-10T09:50:56Z |
A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression
|
Liu, T.-T.;Rabaey, J.M.; Liu, T.-T.; Rabaey, J.M.; TSUNG-TE LIU |
| 臺大學術典藏 |
2019-10-31T07:12:33Z |
A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting
|
HSIN-SHU CHEN;Wen-Jong Wu;Micka?l Lallart;Hsin-Shu Chen;Kai-Ren Cheng; Kai-Ren Cheng; Hsin-Shu Chen; Micka?l Lallart; Wen-Jong Wu; HSIN-SHU CHEN |
| 臺大學術典藏 |
2020-01-17T07:48:26Z |
A 0.25�gm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting
|
WEN-JONG WU;Wu, W.-J.;Lallart, M.;Chen, H.-S.;Cheng, K.-R.; Cheng, K.-R.; Chen, H.-S.; Lallart, M.; Wu, W.-J.; WEN-JONG WU |
| 國立臺灣科技大學 |
2010-03 |
A 0.3 V Cross-Coupled VCO Using Dynamic Threshold MOSFET
|
Sheng-Lyang Jang;Chuang-Jen Huang;Ching-Wen Hsue;Chia-Wei Chang |
| 朝陽科技大學 |
2021-10-02 |
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications
|
Lin,Jin-Fa; Tsai, Chang-Ming; Tsai, Ming-Yan; Hsia, Shih-Chang; Morsalin, S. M. Salahuddin; Sheu, Ming-Hwa; 林進發 |
| 國立臺灣大學 |
2004 |
A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-μm CMOS technology
|
Tsai, Ming-Da; Wang, Huei |
| 臺大學術典藏 |
2020-06-11T06:16:48Z |
A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillator
|
Chang, C.-K.;Tsai, Y.-K.;Cheng, K.-H.;Lu, L.-H.; Chang, C.-K.; Tsai, Y.-K.; Cheng, K.-H.; Lu, L.-H.; LIANG-HUNG LU |
| 國立交通大學 |
2015-07-21T08:29:40Z |
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
|
Lu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Ya-Ping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin |
| 臺大學術典藏 |
2020-06-11T06:31:42Z |
A 0.33 V 683 μW K-band transformer-based receiver front-end in 65 nm CMOS technology
|
Cheng, J.-H.;Hsieh, C.-L.;Wu, M.-H.;Tsai, J.-H.;Huang, T.-W.; Cheng, J.-H.; Hsieh, C.-L.; Wu, M.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
|
Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立臺灣科技大學 |
2010 |
A 0.35 mu m CMOS divide-by-2 quadrature injection-locked frequency divider based on voltage-current feedback topology
|
Jang, S.L.;Liu, C.C.;Yang, R.K.;Shih, C.C.;Chang, C.W.;Yeh, H.A. |
