| 國立中山大學 |
2001-09 |
A 1.0 GHz clock generator design with a negative delay using a single-shot locking method
|
C.C. Wang;Y.L. Tseng;R.S. Kao |
| 臺大學術典藏 |
2018-09-10T09:16:57Z |
A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition
|
LIANG-GEE CHEN; Chen, L.-G.; Tsai, C.-Y.; Lee, Y.-J.; Chen, C.-T. |
| 國立成功大學 |
2023 |
A 1.0�fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process
|
Wang, C.-C.;Sangalang, R.G.B.;Tseng, I.-T.;Chiu, Y.-J.;Lin, Y.-C.;Jose, O.L.J.A. |
| 國立交通大學 |
2020-10-05T02:02:22Z |
A 1.1-3.1-GHz Tunable Quadruplexer with Compact Size and Bandwidth Control
|
Chi, Pei-Ling; Chi, Yu-Wen; Yang, Tao |
| 臺大學術典藏 |
2020-04-28T07:12:59Z |
A 1.1-V CMOS frequency synthesizer with pass-transistor-logic prescaler for U-NII band system
|
Cheng, J.-L.; Wang, C.-S.; Li, W.-C.; Wang, C.-K.; WEI-CHANG LI |
| 國立交通大學 |
2019-12-13T01:12:52Z |
A 1.16-3.89-GHz Tunable Six-Channel Diplexer with Compact Size and High Isolation
|
Chi, Pei-Ling; Chiou, Ching-Kai |
| 臺大學術典藏 |
2022-02-14T23:56:07Z |
A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices
|
Yu, Sheng Jung; Lee, Yu Chi; CHIA-HSIANG YANG |
| 國立臺灣大學 |
2004 |
A 1.1G MAC/s Sub-Word-Parallel Digital Signal Processor for Wireless Communication Applications
|
Huang, Yuan-Hao; Ma, Hsi-Pin; Liou, Ming-Luen; Chiueh, Tzi-Dar |
| 國立中山大學 |
2005-08 |
A 1.1V 25μW Sigma-Delta modulator
|
Shu-Ting Yang;Jyi-Tsong Lin |
| 國立臺灣大學 |
2007 |
A 1.1V Low Phase Noise CMOS Quadrature LC VCO with 4-Way Center-tapped Inductor
|
Upadhyayal, Parag; Heol, Deukhyoun; Rector, David M.; Chen, Yi-Jan Emery |
| 國立高雄第一科技大學 |
2014.01 |
A 1.1~2.4 GHz Broadband QVCO with 74% Fractional Bandwidth for DVB Tuner Applications
|
Peng, Kang-Chun;Liu, Gi-Horng |
| 國立中山大學 |
2004 |
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications
|
C.C. Wang;Y.L. Tseng;H.C. She;R. Hu |
| 國立中山大學 |
2004-12 |
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications
|
C.C. Wang;Y.L. Tseng;H.C. She;R. Hu |
| 國立中山大學 |
2002-09 |
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications
|
C.C. Wang;H.C. She;R. Hu |
| 國立交通大學 |
2014-12-08T15:09:50Z |
A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 mu m CMOS
|
Kuo, Ming-Ching; Kao, Shiau-Wen; Chen, Chih-Hung; Hung, Tsun-Shuen; Shih, Yi-Shing; Yang, Tzu-Yi; Kuo, Chien-Nan |
| 臺大學術典藏 |
2018-09-10T09:22:32Z |
A 1.2 V 15–32?GHz low-power single-balanced gate mixer with a miniature rat-race hybrid
|
Chung-Chun Chen;Chun-Hsien Lien;Hen-Wai Tsao;Huei Wang; Chung-Chun Chen; Chun-Hsien Lien; Hen-Wai Tsao; Huei Wang; HEN-WAI TSAO; HUEI WANG |
| 國立成功大學 |
2018-05-29 |
A 1.2 V 490 μW Sub-GHz UWB CMOS LNA with Current Reuse Negative Feedback
|
Chen, Wei-Wei; Yang, Shang-De; Cheng, Kuang-Wei |
| 國立成功大學 |
2018 |
A 1.2 v 490 μw Sub-GHz UWB CMOS LNA with Current Reuse Negative Feedback
|
Chen, W.-W.;Yang, S.-D.;Cheng, K.-W. |
| 淡江大學 |
2001-09 |
A 1.2 V 500 MHz 32-bit carry-lookahead adder
|
鄭國興; Cheng, Kuo-hsing; Lee, Wen-shiuan; Huang, Yung-chong |
| 國立交通大學 |
2014-12-08T15:27:23Z |
A 1.2 V CMOS four-quadrant analog multiplier
|
Hsiao, SY; Wu, CY |
| 淡江大學 |
1996-10-13 |
A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic
|
鄭國興; Cheng, Kuo-hsing; Yee, Liow yu |
| 淡江大學 |
1997-12-15 |
A 1.2 V low-power TSPC complementary pass transistor logic
|
鄭國興; Cheng, Kuo-hsing; Chen, Jian-hung |
| 國立成功大學 |
2002-09 |
A 1.2 V rail-to-rail analog CMOS rank-order filter with k-WTA capability
|
Hung, Yu-Cherng; Liu, Bin-Da |
| 國立臺灣大學 |
2007 |
A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- μm CMOS Technology
|
Cho, Lan-Chou; Lee, Chihun; Liu, Shen-Iuan |
| 國立交通大學 |
2014-12-08T15:28:31Z |
A 1.2-V 5.2-mW 20-30-GHz Wideband Receiver Front-End in 0.18-mu m CMOS
|
Li, Chun-Hsing; Kuo, Chien-Nan; Kuo, Ming-Ching |
