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Institution Date Title Author
國立臺灣大學 2009 Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide Lin, C.H.; Kuo, J.B.
國立臺灣大學 2008 Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application Chung, B.; Kuo, J.B.
國立臺灣大學 2008 Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect Su, V.C.; Lin, I.S.; Kuo, J.B.; Lin, G.S.; Chen, D.; Yeh, C.S.; Tsai, C.T.; Ma, M.
國立臺灣大學 2007 Narrow Band Gap Semiconductor Lin, H. H.; Kuo, J. B.
國立臺灣大學 2007 Narrow Bandgap Semiconductor Lin, H. H.; Kuo, J. B.
國立臺灣大學 2006-02 Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1 nm) gate oxide Lin, C.H.; Kuo, J.B.; Su, K.W.; Liu, S.
國立臺灣大學 2006 Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation Lin, Yu-Sheng; Lin, Chia-Hong; Kuo, J.B.; Su, Ke-Wei
國立臺灣大學 2006 Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation Chen, Chien-Chung; Kuo, J.B.; Su, Ke-Wei; Liu, Sally
國立臺灣大學 2005-05 Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications Liu, G.Y.; Wang, N.C.; Kuo, J.B.
臺大學術典藏 2005-05 Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications Liu, G.Y.; Wang, N.C.; Kuo, J.B.; Liu, G.Y.; Wang, N.C.; Kuo, J.B.

Showing items 11-20 of 128  (13 Page(s) Totally)
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