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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"kuo j b"的相關文件
顯示項目 11-20 / 128 (共13頁) << < 1 2 3 4 5 6 7 8 9 10 > >> 每頁顯示[10|25|50]項目
| 國立臺灣大學 |
2009 |
Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide
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Lin, C.H.; Kuo, J.B. |
| 國立臺灣大學 |
2008 |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application
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Chung, B.; Kuo, J.B. |
| 國立臺灣大學 |
2008 |
Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect
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Su, V.C.; Lin, I.S.; Kuo, J.B.; Lin, G.S.; Chen, D.; Yeh, C.S.; Tsai, C.T.; Ma, M. |
| 國立臺灣大學 |
2007 |
Narrow Band Gap Semiconductor
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Lin, H. H.; Kuo, J. B. |
| 國立臺灣大學 |
2007 |
Narrow Bandgap Semiconductor
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Lin, H. H.; Kuo, J. B. |
| 國立臺灣大學 |
2006-02 |
Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1 nm) gate oxide
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Lin, C.H.; Kuo, J.B.; Su, K.W.; Liu, S. |
| 國立臺灣大學 |
2006 |
Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation
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Lin, Yu-Sheng; Lin, Chia-Hong; Kuo, J.B.; Su, Ke-Wei |
| 國立臺灣大學 |
2006 |
Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation
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Chen, Chien-Chung; Kuo, J.B.; Su, Ke-Wei; Liu, Sally |
| 國立臺灣大學 |
2005-05 |
Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications
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Liu, G.Y.; Wang, N.C.; Kuo, J.B. |
| 臺大學術典藏 |
2005-05 |
Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications
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Liu, G.Y.; Wang, N.C.; Kuo, J.B.; Liu, G.Y.; Wang, N.C.; Kuo, J.B. |
顯示項目 11-20 / 128 (共13頁) << < 1 2 3 4 5 6 7 8 9 10 > >> 每頁顯示[10|25|50]項目
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