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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"wu chung yu"的相關文件
顯示項目 211-219 / 219 (共5頁)
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| 淡江大學 |
1996-05 |
True-single-phase all-N-logic differential logic (TADL) for very high-speed complex VLSI
|
Huang, Hong-yi; 鄭國興; Cheng, Kuo-hsing; Chu, Yuan-hua; Wu, Chung-yu |
| 淡江大學 |
1995-04-30 |
Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits
|
Huang, Hong-yi; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan; Chu, Yuan-hua; Wu, Tain-shun; Wu, Chung-yu |
| 淡江大學 |
1995-04-30 |
A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications
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Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing; Lu, Jr-houng |
| 淡江大學 |
1994-05-30 |
Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit
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Tseng, Yuh-kuang; 鄭國興; Cheng, Kuo-hsing; Wu, Chung-yu |
| 淡江大學 |
1993-01 |
Analysis and design of a new race-free four-phase CMOS logic
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Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan |
| 淡江大學 |
1992-05 |
High-speed four-phase CMOS logic for complex high-speed VLSI
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Wu, Chung-yu; Cheng, Kuo-hsing; Wang, Jinn-shyan |
| 淡江大學 |
1991-09 |
Latched CMOS differential logic(LCDL)for complex high-speed VLSI
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Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing |
| 淡江大學 |
1989-09 |
Latched CMOS differential logic(LCDL)for complex high-speed VLSI
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Wu, Chung-yu; Cheng, Kuo-hsing |
| 淡江大學 |
1912-01 |
Latched CMOS differential logic(ALCDL)and its application in the design of high-speed parallel multipliers
|
Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing |
顯示項目 211-219 / 219 (共5頁)
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