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Institution	Date	Title	Author
國立中山大學	2006	Gate-controlled spin splitting in GaN/AlN quantum wells	Ikai Lo;W.T. Wang;M.H. Gao;J.K. Tsai;S.F. Tsay;J.C. Chiang
國立中山大學	2006	Gate-controlled Spin Splitting in GaN/AlN Quantum Wells	Ikai Lo;W.T. Wang;M.H. Gau;S.F. Tsay;Jih-Chen Chiang
國立中山大學	2006	Gate-Controlled Spin Splitting in GaN/AlN Quantum Wells	Ikai Lo;W.T. Wang;M.H. Gau;J.K. Tsai;S.F. Tsay;J.C. Chiang
國立交通大學	2014-12-08T15:17:41Z	Gate-controlled ZnO nanowires for field-emission device application	Li, SY; Lee, CY; Lin, P; Tseng, TY
國立交通大學	2014-12-08T15:31:00Z	Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack	Cheng, C. H.; Chou, K. I.; Chin, A.
國立交通大學	2014-12-08T15:47:59Z	Gate-First TaN/La(2)O(3)/SiO(2)/Ge n-MOSFETs Using Laser Annealing	Chen, W. B.; Wu, C. H.; Shie, B. S.; Chin, Albert
中華大學	2010	Gate-First TaN/La2O3/SiO2/Ge n-MOSFETs Using Laser Annealing	吳建宏; rossiwu
國立交通大學	2019-04-02T06:00:27Z	Gate-First TaN/La2O3/SiO2/Ge n-MOSFETs Using Laser Annealing	Chen, W. B.; Wu, C. H.; Shie, B. S.; Chin, Albert
國立交通大學	2019-04-02T05:58:20Z	Gate-induced localized states in graphene: Topological nature in their formation	Wang, L. Y.; Chang, Che-Yuan; Chu, C. S.
臺大學術典藏	2018-09-10T06:02:15Z	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology	B. Chung; J. B. Kuo; JAMES-B KUO

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