| 國立交通大學 |
2014-12-08T15:25:51Z |
Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces
|
Chang, WJ; Ker, MD |
| 中原大學 |
1998-11-10 |
Layout structure for improving resistance uniformity of a polysilicon resistor
|
Shen-Wen Cheng;Chun-Lin Cheng |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Layout Styles to Improve CDM ESD Robustness of Integrated Circuits in 65-nm CMOS Process
|
Ker, Ming-Dou; Lin, Chun-Yu; Chang, Tang-Long |
| 國立臺灣大學 |
1985-09 |
Layout System Vol. 1:Computer-Aided VLSI Routing Design
|
Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立臺灣大學 |
1985 |
Layout System Vol. 2:Symbolic Layout and Circuit Compaction for CMOS IC Design
|
Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立臺灣大學 |
1985-09 |
Layout System Vol. 3:Design and Implementation of a Design Rule Checking System for VLSI Design
|
Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立臺灣大學 |
1986-09 |
Layout System Vol. 4:an Automatic Placement System for VLSI Layouts
|
Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung |
| 國立交通大學 |
2014-12-08T15:25:40Z |
Layout techniques for on-chip interconnect inductance reduction
|
Tu, SW; Jou, JY; Chang, YW |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Layout techniques for on-chip interconnect inductance reduction
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 義守大學 |
2011 |
Layout 設計與電磁相容之研究
|
陳安吉; An-Chi chen |
| 國立中山大學 |
2006-08 |
Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis
|
X.L. Li;S.J. Wang;K.S.M. Li |
| 國立中山大學 |
2006-08 |
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage
|
K.L. Peng;S.J. Wang;K.S.M. Li |
| 國立交通大學 |
2019-10-05T00:09:48Z |
Layout-Based Dual-Cell-Aware Tests
|
Wu, Tse-Wei; Lee, Dong-Zhen; Wu, Kai-Chiang; Huang, Yu-Hao; Chen, Ying-Yen; Chen, Po-Lin; Chern, Mason; Lee, Jih-Nung; Kao, Shu-Yi; Chao, Mango C. -T. |
| 國立交通大學 |
2017-04-21T06:56:48Z |
Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults-From Device to Circuit Level
|
Huang, Hsuan-Ming; Wen, Charles H. -P. |
| 臺大學術典藏 |
2018-09-10T15:33:11Z |
Layout-Dependent Effects-Aware Analytical Analog Placement
|
Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG |
| 國立交通大學 |
2014-12-08T15:27:35Z |
Layout-Dependent Stress Effect on High-Frequency Characteristics and Flicker Noise in Multifinger and Donut MOSFETs
|
Yeh, Kuo-Liang; Guo, Jyh-Chyurn |
| 臺大學術典藏 |
2018-09-10T15:23:14Z |
Layout-dependent-effects-aware analytical analog placement
|
Ou, H.-C.;Tseng, K.-H.;Liu, J.-Y.;Wu, I.-P.;Chang, Y.-W.; Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2022-02-21T23:31:24Z |
LayoutTransformer: Scene Layout Generation with Conceptual and Spatial Diversity
|
Yang, Cheng Fu; Fan, Wan Cyuan; Yang, Fu En; Wang, Yu Chiang Frank |
| 臺大學術典藏 |
2021-01-04T05:52:14Z |
Laypeople's source selection in online health information-seeking process
|
Chi, Y.;He, D.;Jeng, W.; Chi, Y.; He, D.; Jeng, W.; Wei Jeng |
| 國立成功大學 |
2011-07-31 |
LAZ1021鎂鋰合金延脆轉換特性之應變速率及織構效應探討
|
黃鶉亦; Huang, Chun-Yi |
| 國立成功大學 |
2011-07-07 |
LAZ1021鎂鋰合金延脆轉換特性之應變速率及織構效應探討
|
黃鶉亦; Huang, Chun-Yi |
| 國立臺灣大學 |
2004 |
Lazarillo de Tormes: variantes de la t?cnica narrativa de la novela al cine
|
Luisa Shu-Ying Chang |
| 臺大學術典藏 |
2018-09-10T04:52:34Z |
Lazarillo de Tormes: Variantes de la t?cnica narrativa de la novela al cine
|
SHU-YING CHANG; SHU-YING CHANG; SHU-YING CHANG |
| 臺大學術典藏 |
2020-06-04T07:49:00Z |
Lazy decision diagrams for word-level model manipulation in software verification
|
Wang, F.; Wang, F.; FARN WANG |
| 亞洲大學 |
2006 |
Lazy Indirect Illumination Evaluation Using Barycentric Coordinates
|
蔡淵裕;Tsai, Yuan-Yu |
