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Institution	Date	Title	Author
南台科技大學	1995-01	Performance-Directed Compaction for VLSI Symbolic Layout	Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; Ting-Chun Chang;王立洋
國立成功大學	2012-11	Performance-driven Analog Placement Considering Monotonic Current Paths	Wu, Po-Hsun; Lin, Mark Po-Hung; Chen, Yang-Ru; Chou, Bing-Shiun; Chen, Tung-Chieh; Ho, Tsung-Yi; Liu, Bin-Da
國立交通大學	2014-12-08T15:21:46Z	Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay	Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang
國立交通大學	2014-12-08T15:22:04Z	Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay	Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang
元智大學	2009-04	Performance-driven dual-rail insertion for chip-level pre-fabricated design	陳福偉; 劉一宇
元智大學	2010-12	Performance-driven dual-rail routing architecture for structured ASIC design style	Fu-Wei Chen; Yi-Yu Liu
南台科技大學	1993	Performance-Driven Global Routing Based on Simulated Evolution	Lih-Yang Wang; Bin-Da Liu; Yen-Tai Lai; Ming-Yuan Yeh; 王立洋;劉濱達
中原大學	2006-08	Performance-Driven Global Routing in the Present of Obstacles	Wu, Wei-Yu;Hsieh, Tsai-Ming;Huang, Hsin-Hsiung
臺大學術典藏	2018-09-10T04:12:52Z	Performance-driven placement for dynamically reconfigurable FPGAs	Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG
國立臺灣大學	2002	Performance-driven placement for dynamically reconfigurable FPGAs	Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen

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