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Institution	Date	Title	Author
國立成功大學	2002-09	A 0.5 mu m concurrent testable chip of a fifth-order g(m)-C filter	Lee, Kuen-Jong; Wang, Wei-Chiang
淡江大學	2011-01	A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process	Yang, Wei-Bin; Liao, Chao-Cheng; Liang, Yung-Chih
國立交通大學	2014-12-08T15:40:05Z	A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications	Chen, Tsan-Wen; Yu, Jui-Yuan; Yu, Chien-Ying; Lee, Chen-Yi
國立高雄師範大學	2009-08	A 0.5 V Phase-Locked Loop in 90nm CMOS Process	Kuo-Hsing Cheng;Jing-Shiuan Huang;Yu-Chang Tsai;Chao-Chang Chiu;Yu-Lung Lo; 羅有龍
臺大學術典藏	2003-06	A 0.5-14-GHz 10.6-dB CMOS cascode distributed amplifier	Liu, Ren-Chieh; Lin, Chin-Shen; Deng, Kuo-Liang; Wang, Huei; Liu, Ren-Chieh; Lin, Chin-Shen; Deng, Kuo-Liang; Wang, Huei
國立臺灣大學	2003-06	A 0.5-14-GHz 10.6-dB CMOS cascode distributed amplifier	Liu, Ren-Chieh; Lin, Chin-Shen; Deng, Kuo-Liang; Wang, Huei
元智大學	2016-06-23	A 0.5-3.5GHZ Wideband CMOS LNA for LTE Application	Wei-Rern Liao; Jeng-Rern Yang
國立高雄師範大學	2011-03	A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip	Kuo-Hsing Chen;Yu-Chang Tsai;Yu-Lung Lo;Jing-Shiuan Huang; 羅有龍
國立交通大學	2018-08-21T05:54:15Z	A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist	Wu, Shang-Lin; Li, Kuang-Yu; Huang, Po-Tsang; Hwang, Wei; Tu, Ming-Hsien; Lung, Sheng-Chi; Peng, Wei-Sheng; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te
臺大學術典藏	2019-10-24T08:43:09Z	A 0.5-V 400-MHz Transceiver Using Injection-Locked Techniques in 180-nm CMOS	林宗賢;TSUNG-HSIEN LIN;T.-H. Lin;Y.-L. Tsai;T.-W. Wang;C.-R. Lee; C.-R. Lee; T.-W. Wang; Y.-L. Tsai; T.-H. Lin; TSUNG-HSIEN LIN; 林宗賢

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