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Showing items 90686-90695 of 2346788  (234679 Page(s) Totally)
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Institution Date Title Author
國立交通大學 2014-12-08T15:34:48Z A 0.75-2.67 GHz 5-bit Vector-Sum Phase Shifter Yan, Tzu-Chao; Lin, Wei-Zhen; Kuo, Chien-Nan
國立東華大學 2007-09 A 0.7V 3-5GHz CMOS Low Noise Amplifier for Ultra-wideband Applications 翁若敏; Weng, Ro-Min; Hsiao, Chih-Lung ; Lee, Wei-Chi
國立高雄師範大學 2008-06 A 0.7V Low-Voltage Folded-Cascode Uwblana with a Resistive Feedback Ruey-Lue Wang;Cheng-Lin Huang;Shih-Chih Chen;Jui-Hao Shang;Cheng-Lung Tsai; 王瑞祿
國立臺灣大學 2006 A 0.7–2-GHz Self-Calibrated Multiphase Delay-Locked Loop Chang, Hsiang-Hui; Chang, Jung-Yu; Kuo, Chun-Yi; Liu, Shen-Iuan
國立臺灣大學 2004-12 A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI Chen, H.P.; Kuo, J.B.
臺大學術典藏 2002-08 A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan
國立臺灣大學 2002-08 A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture Chang, Hsiang-Hui; Chen, Shang-Ping; Cheng, Kuang-Wei; Liu, Shen-Iuan
臺大學術典藏 2004-09 A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator Liu, Tsung-Te; Wang, Chorng-Kuang; Liu, Tsung-Te; Wang, Chorng-Kuang
國立臺灣大學 2004-09 A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator Liu, Tsung-Te; Wang, Chorng-Kuang
國立成功大學 2022-10 A 0.8-mu W and 74-dB High-Pass Sigma-Delta Modulator With OPAMP Sharing and Noise-Coupling Techniques for Biomedical Signal Acquisition Lee;Shuenn-Yuh;Lee;Hao-Yun;Kung;Chia-Ho;Su;Po-Han;Chen;Ju-Yi

Showing items 90686-90695 of 2346788  (234679 Page(s) Totally)
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