| 國立交通大學 |
2014-12-08T15:09:28Z |
A 1.9mW portable ADPLL-based frequency synthesizer for high speed clock generation
|
Chang, Ming-Hung; Yang, Zong-Xi; Hwang, Wei |
| 臺大學術典藏 |
2020-02-26T07:30:06Z |
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Huang S.-A; Chang K.-C; HORNG-HUEI LIOU; Yang C.-H. |
| 臺大學術典藏 |
2018 |
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
|
Yang C.-H.; HORNG-HUEI LIOU; Chang K.-C.; Huang S.-A.; Huang S.-A.;Chang K.-C.;Horng-Huei Liou;Yang C.-H. |
| 中華大學 |
2005 |
A 10 Bit 40-MS/s Pipelined Analog-to-Digital Converter for IEEE 802.11a WLAN Systems
|
田慶誠; Tien, Ching-Cheng |
| 中華大學 |
2006 |
A 10 Bit 40-MS/s Pipelined Analog-to-Digital Converter for IEEE 802.16 WiMAX Systems
|
田慶誠; Tien, Ching-Cheng |
| 中華大學 |
2007 |
A 10 Bit 40-MS/s Pipelined Analog-to-Digital Converter for WLAN Systems
|
田慶誠; Tien, Ching-Cheng |
| 國立交通大學 |
2014-12-08T15:30:06Z |
A 10 Gb/s Adaptive Cable Equalizer Using Phase Detection Technique in 0.13 mu m CMOS Technology
|
Chen, Kuang-Ren; Tsai, Chia-Ming; You, Sheng-Kai; Li, An-Siou; Chen, Wen-Tsao |
| 臺大學術典藏 |
2004-05 |
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier
|
Tsai, Hung-Chieh; Yeh, Jyh-Yih; Tu, Wei-Hsuan; Lee, Tai-Cheng; Wang, Chorng-Kuang; Tsai, Hung-Chieh; Yeh, Jyh-Yih; Tu, Wei-Hsuan; Lee, Tai-Cheng; Wang, Chorng-Kuang |
| 國立臺灣大學 |
2004-05 |
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier
|
Tsai, Hung-Chieh; Yeh, Jyh-Yih; Tu, Wei-Hsuan; Lee, Tai-Cheng; Wang, Chorng-Kuang |
| 國立交通大學 |
2014-12-08T15:25:19Z |
A 10 GHz low power CMOS quadrature voltage-controlled oscillator
|
Tarng, Shih-Hao; Jou, Christina F. |
| 臺大學術典藏 |
2009 |
A 10 GHz Phase-Locked Loop With a Compact Low-Pass Filter in 0.18 um CMOS
|
Li, Sin-Jhih; Hsieh, Hsieh-Hung; Lu, Liang-Hung; Li, Sin-Jhih; Hsieh, Hsieh-Hung; Lu, Liang-Hung |
| 國立臺灣大學 |
2009 |
A 10 GHz Phase-Locked Loop With a Compact Low-Pass Filter in 0.18 um CMOS
|
Li, Sin-Jhih; Hsieh, Hsieh-Hung; Lu, Liang-Hung |
| 臺大學術典藏 |
2018-09-10T07:43:05Z |
A 10 GHz phase-locked loop with a compact low-pass filter in 0.18 μm CMOS
|
S.-J. Li;H.-H. Hsieh;L.-H. Lu; S.-J. Li; H.-H. Hsieh; L.-H. Lu; LIANG-HUNG LU |
| 臺大學術典藏 |
2009 |
A 10 GHz phase-locked loop with a compact low-pass filter in 0.18 μm CMOS
|
Li, S.-J.;Hsieh, H.-H.;Lu, L.-H.; Li, S.-J.; Hsieh, H.-H.; Lu, L.-H.; LIANG-HUNG LU |
| 國立交通大學 |
2014-12-08T15:15:22Z |
A 10 similar to 18GHz wide-band transfonner feedback LNA
|
Chiang, Pei-Yuan; Jou, Christina. F.; Wu, Hui-I; Huang, Zhe-Yang |
| 中國醫藥大學 |
2012-12-08 |
A 10 year-old boy bilious vomiting and abdominal pain for 2 weeks
|
黃鈺婷(Yu-Ting Huang);陳安琪(An-Chyi Chen);吳淑芬(Shu-Fen Wu);陳偉德(Walter Chen);黃鈺婷(Yu-Ting Huang) |
| 國立交通大學 |
2014-12-08T15:14:09Z |
A 10-110 GHz fundamental/harmonic rat-race mixer
|
Chi, Chun-Hsiang; Wu, Chung-Hung; Wang, Wei-Ting; Lai, Chi-Hau; Niu, Dow-Chih; Chang, Chi-Yang |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 10-20 Gb/s CDR circuit with 6200ppm frequency tracking
|
Huang, C.-C.;Tseng, K.-W.;Liu, S.-I.; Huang, C.-C.; Tseng, K.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 國立臺灣大學 |
2008-07 |
A 10-35 GHz low power bulk-driven mixer using 0.13-μm CMOS process
|
Kuo, Chun-Lin; Huang, Bo-Jr; Kuo, Che-Chung; Lin, Kun-You; Wang, Huei |
| 國立成功大學 |
2009-02 |
A 10-40 GHZ, Broadband Subharmonic Monolithic Mixer in 0.18 mu m CMOS Technology
|
Lin, Chih-Ming; Lin, Hua-Kuei; Lai, Yu-Ann; Chang, Chieh-Pin; Wang, Yeong-Her |
| 國立交通大學 |
2014-12-08T15:03:43Z |
A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCES
|
CHIN, SY; WU, CY |
| 臺大學術典藏 |
2018-09-10T09:21:52Z |
A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC
|
Tseng, C.-J.;Chen, H.-W.;Shen, W.-T.;Cheng, W.-C.;Chen, H.-S.; Tseng, C.-J.; Chen, H.-W.; Shen, W.-T.; Cheng, W.-C.; Chen, H.-S.; HSIN-SHU CHEN |
| 國立暨南國際大學 |
2013 |
A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs
|
蕭敬民; Hsiao, CM |
| 國立暨南國際大學 |
2013 |
A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs
|
尹邦嚴; Yin, PY |
| 國立成功大學 |
2019 |
A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC
|
Hu, Hu H.-J.;Cheng, Y.-S.;Chang, S.-J. |
