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Institution	Date	Title	Author
國立臺灣科技大學	2018	A 12-bit 10-MS/s SAR ADC with a binary-window DAC switching scheme in 180-nm CMOS	Chung Y.-H.; Yen C.-W.; Tsai P.-K.
國立臺灣科技大學	2019	A 12-Bit 100-MS/s Subrange SAR ADC with a Foreground Offset Tracking Calibration Scheme	Chung, Y.-H.;Hsu, Y.-M.
國立臺灣科技大學	2018	A 12-bit 160-MS/s ping-pong subranged-SAR ADC in 65nm CMOS	Chung, Y.-H.;Hsu, Y.-M.;Yen, C.-W.;Rih, W.-S.
國立臺灣科技大學	2019	A 12-bit 20-MS/s SAR ADC with Fast-Binary-Window DAC Switching in 180nm CMOS	Chung, Y.-H.;Lin, Y.-S.;Zeng, Q.-F.
臺大學術典藏	2020-06-11T06:48:28Z	A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique	Hu, Y.-S.;Lin, K.-Y.;Chen, H.-S.; Hu, Y.-S.; Lin, K.-Y.; Chen, H.-S.; HSIN-SHU CHEN
臺大學術典藏	2018-09-10T15:00:41Z	A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique	C-Y Lin;T-C Lee; C-Y Lin; T-C Lee; TAI-CHENG LEE
臺大學術典藏	2020-06-11T06:34:56Z	A 12-bit 3.4 MS/s two-step cyclic time-domain ADC in 0.18-μm CMOS	Chen, L.-J.;Liu, S.-I.; Chen, L.-J.; Liu, S.-I.; SHEN-IUAN LIU
國立成功大學	2014-03	A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD <-61dB at 2.8 GS/s With DEMDRZ Technique	Lin, Wei-Te; Huang, Hung-Yi; Kuo, Tai-Haur
國立成功大學	2017	A 12-bit 40-MS/s calibration-free SAR ADC	Hsu, C.-W.;Chang, L.-J.;Huang, C.-P.;Chang, S.-J.
國立臺灣科技大學	2018	A 12-bit 40-MS/s SAR ADC with a Fast-Binary-Window DAC Switching Scheme	Chung Y.-H.; Yen C.-W.; Tsai P.-K.; Chen B.-W.

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