|
English
|
正體中文
|
简体中文
|
Total items :2853524
|
|
Visitors :
45214391
Online Users :
884
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Title
|
Showing items 91431-91440 of 2346260 (234626 Page(s) Totally)
<< < 9139 9140 9141 9142 9143 9144 9145 9146 9147 9148 > >>
View [10|25|50] records per page
| 國立臺灣師範大學 |
2014-10-30T09:28:44Z |
A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process
|
Yung-Nien Jen; Jeng-Han Tsai; Chung-Te Peng; Tian-Wei Huang |
| 淡江大學 |
2005-03 |
A 20 Years Overview and Prospect of Interpretive Research in Taiwan: 1984-2003
|
陳維立; Wu, H. C.; Chen, W. J. |
| 臺大學術典藏 |
2021-09-02T00:05:04Z |
A 20-43 GHz Low Noise GaAs Downconverter with Gbps Data-Links for Full 5G K/Ka-Band Backhauls
|
Chen C.-N;Kuo T.-Y;Wang H.; Chen C.-N; Kuo T.-Y; Wang H.; HUEI WANG |
| 臺大學術典藏 |
2021-03-12T08:41:03Z |
A 20-Gb/s 1: 2 demultiplexer with capacitive-splitting current-mode-logic latches
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
| 國立臺灣大學 |
2007 |
A 20-Gb/s 1:2 Demultiplexer with capacitive-splitting current-mode-logic latches
|
Chien, Jun-Chau; Lu, Liang-Hung |
| 國立臺灣大學 |
2005-06 |
A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-/spl mu/m CMOS technology
|
Lee, Jri; Ding, Jian-Yu; Cheng, Tuan-Yi |
| 臺大學術典藏 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri; Lee, Jri |
| 國立臺灣大學 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri |
| 臺大學術典藏 |
2018-09-10T06:03:22Z |
A 20-Gb/s Adaptive Equalizer in 0.13 μm CMOS Technology
|
Jri Lee; JRI LEE |
| 國立臺灣大學 |
2006 |
A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology
|
Lee, Jri |
Showing items 91431-91440 of 2346260 (234626 Page(s) Totally)
<< < 9139 9140 9141 9142 9143 9144 9145 9146 9147 9148 > >>
View [10|25|50] records per page
|
