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Institution Date Title Author
國立中山大學 2003-06-25 VLIW DSP架構之增進指令並行度之向量化運算機制 楊得鑫
中華大學 2004 VLIW Processor with Embedded Watchdog Processor for Control Flow Error Detection 陳永源; Chen, Yung-Yuan
淡江大學 2024-07-31T04:08:27Z Vloggers and consumer choices in the hotel and hospitality sector: The double-edged sword of discounts Ni, Yensen
國立成功大學 2005-04 VLSI architectural design tradeoffs for sliding-window Log-MAP decoders Wu, Chien-Ming; Shieh, Ming-Der; Wu, Chien-Hsing; Hwang, Yin-Tsung; Chen, Jun-Hong
國立成功大學 2002-08 VLSI architecture and implementation for speech recognizer based on discriminative Bayesian neural network Wang, Jhing-Fa; Wang, Jia-Ching; Suen, An-Nan; Wu, Chung-Hsien; Li, Fan-Min
臺大學術典藏 2018-09-10T04:07:51Z VLSI architecture design and implementation for TWOFISH block cipher Lai, Y.-K.; Chen, L.-G.; Lai, J.-Y.; Parng, T.-M.; LIANG-GEE CHEN
國立臺灣大學 2001-07-31 VLSI Architecture Design and Implementation of IF and Baseband Analog Front End for Digital Multimedia Wireless Receiver (II) 汪重光
亞洲大學 2002-05-16 VLSI ARCHITECTURE DESIGN FOR TWOFISH BLOCK CIPHER Li-Chung Chang ;Yeong-Kang Lai; Liang-Gee Chen;Jian-Yi La;Tai-Ming Parng
中國文化大學 1997-06 VLSI Architecture Design of a High Performance Clustering Analyzer 賴茂富
元智大學 Dec-15 VLSI Architecture Design of FM0/Manchester Codec with 100% Hardware Utilization Rate for DSRC-Based Sensor Nodes in ITS Applications Yu-Hsuan Lee; Cheng-Wei Pan; Fang-Hsu Tsai
國立臺灣大學 2008 VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC Chen, Yi-Hau; Chen, Tung-Chien; Chien, Shao-Yi; Huang, Yu-Wen; Chen, Liang-Gee
臺大學術典藏 2018-09-10T14:57:57Z VLSI architecture design of guided filter for 30 frames/s full-HD Video Kao, C.-C.;Lai, J.-H.;Chien, S.-Y.; Kao, C.-C.; Lai, J.-H.; Chien, S.-Y.; SHAO-YI CHIEN
臺大學術典藏 2020-06-16T06:38:08Z VLSI architecture design of layer-based bilateral and median filtering for 4k2k videos at 30fps Tai, M.-Y.;Tu, W.-C.;Chien, S.-Y.; Tai, M.-Y.; Tu, W.-C.; Chien, S.-Y.; SHAO-YI CHIEN
義守大學 2003-10 VLSI architecture design of modified Euclidean algorithm for Reed-Solomon code Y.W. Chang;J.H. Jeng;T.K. Truong
國立交通大學 2014-12-08T15:25:57Z VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders Wang, YY; Peng, YT; Tsai, CJ
臺大學術典藏 2018-09-10T04:07:51Z VLSI architecture design of MPEG-4 shape coding Chang, H.-C.; Chang, Y.-C.; Wang, Y.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN
國立臺灣大學 2002 VLSI architecture design of MPEG-4 shape coding Chang, Hao-Chieh; Chang, Yung-Chi; Wang, Yi-Chu; Chao, Wei-Ming; Chen, Liang-Gee
臺大學術典藏 2018-09-10T07:26:43Z VLSI architecture design of VLC encoder for high data rate video/image coding Chang, Hao-Chieh; Chen, Liang-Gee; Chang, Yung-Chi; Huang, Sheng-Chieh; LIANG-GEE CHEN
臺大學術典藏 2003-08 VLSI architecture for discrete wavelet transform based on B-spline factorization Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學 2003-08 VLSI architecture for discrete wavelet transform based on B-spline factorization Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏 2018-09-10T04:27:42Z VLSI architecture for discrete wavelet transform based on B-spline factorization Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN
臺大學術典藏 2018-09-10T05:15:44Z VLSI architecture for fifting-based shape-adaptive discrete wavelet transform with odd-symmetric filters Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN
國立臺灣大學 2005 VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏 2018-09-10T05:15:44Z VLSI architecture for forward discrete wavelet transform based on B-spline factorization Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN
國立臺灣大學 2005 VLSI Architecture for Lifting-based Shape-Adaptive Discrete Wavelet Transform with Odd-symmetric Filters Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee

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