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Institution	Date	Title	Author
國立交通大學	2014-12-08T15:03:00Z	VLSI cell placement on arbitrarily-shaped rectilinear regions using neural networks with calibration nodes	Chang, RI; Hsiao, PY
國立交通大學	2014-12-08T15:01:53Z	VLSI cell placement on arbitrarily-shaped rectilinear regions using neural networks with calibration nodes - Comments	Huang, KY
國立中山大學	2001-09	VLSI circuit design of 16-Mbps IrDA VFIR transceivers	C.C. Wang;C.W. Chen;Y.L. Huang
國立交通大學	2014-12-08T15:01:29Z	VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps	Chang, RI; Hsiao, PY
國立交通大學	2019-04-02T05:59:32Z	VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps	Chang, RI; Hsiao, PY
臺大學術典藏	2018-09-10T06:32:26Z	VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps	RAY-I CHANG;HSIAO, PY;CHANG, RI; CHANG, RI; HSIAO, PY; RAY-I CHANG
臺大學術典藏	2018-09-10T08:34:15Z	VLSI design and implementation of density-based spike classification for neuroprosthetic applications	Cheng, L.-F.;Chen, T.-C.;Chen, L.-G.; Cheng, L.-F.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN
國立聯合大學	2004	VLSI Design and Implementation of The Re-configurable 2-D Von Neumann Cellular Automata Bases Generator for The Image Processing Applications	陳榮堅, 賴瑞麟
國立交通大學	2014-12-08T15:46:11Z	VLSI design for high-speed LZ-based data compression	Chen, JM; Wei, CH
國立中山大學	1998-06	VLSI design of A 1.0 GHz 0.6-µm 8-Bit CLA using PLA-styled all-N-transistor Logic	C.C. Wang;K.C. Tsai

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