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Institution	Date	Title	Author
臺北醫學大學	2005	A bibliometric study of the trend in documents published in a category of public, environmental & occupational.	邱文達; Jhou SL;Chiu WT;Feng YT;Lin IH;Su CT;HoL YS
臺大學術典藏	1993-05	A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI	Kuo, J.B.; Chen, H.P.; Huang, H.J.; Kuo, J.B.; Chen, H.P.; Huang, H.J.; KuoJB
國立臺灣大學	1993-05	A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI	Kuo, J.B.; Chen, H.P.; Huang, H.J.
臺大學術典藏	1992-10	A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture	Kuo, J.B.; Liao, H.J.; Chen, H.P.; Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB
國立臺灣大學	1992-10	A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture	Kuo, J.B.; Liao, H.J.; Chen, H.P.
臺大學術典藏	1994-06	A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit	Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB
國立臺灣大學	1994-06	A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit	Kuo, J.B.; Su, K.W.; Lou, J.H.
國立臺灣大學	1991-05	A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for neural network VLSI operating at 77 K	Chou, T.L.; Wong, E.J.; Lee, W.C.; Kuo, J.B.
國立臺灣大學	1991-06	A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for pattern recognition neural network VLSI operating at 77 K	Chou, T.L.; Wong, E.J.; Kuo, J.B.
國立臺灣大學	1996-08	A BiCMOS Limiting Amplifier for SONET OC-3	Huang, C. Y.; Y. C. Peng; 汪重光; Huang, C. Y.; Y. C. Peng; Wang, C. K.

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