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教育部委托研究计画 计画执行:国立台湾大学图书馆
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显示项目 544721-544730 / 2348617 (共234862页)
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每页显示[10|25|50]项目
| 國立交通大學 |
2014-12-08T15:35:55Z |
Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits
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Tsai, Hui-Wen; Ker, Ming-Dou |
| 國立臺灣科技大學 |
2015 |
Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning
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Fang, S.-Y.;Tai, Y.-S.;Chang, Y.-W. |
| 臺大學術典藏 |
2018-09-10T15:23:14Z |
Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning
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Fang, S.-Y.;Tai, Y.-S.;Chang, Y.-W.; Fang, S.-Y.; Tai, Y.-S.; Chang, Y.-W.; YAO-WEN CHANG |
| 國立交通大學 |
2014-12-08T15:06:31Z |
Layout dependence on threshold voltage instability of hydrogenated amorphous silicon thin film transistors
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Tseng, Huai-Yuan; Chiang, Ko-Yu; Lu, Hau-Yan; Kung, Chen-Pang; Chang, Ting-Chang |
| 國立中山大學 |
2007 |
Layout dependence on threshold voltage instability of hydrogenated amorphous silicon thin film transistors
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H.Y. Tseng;K.Y. Chiang;H.Y. Lu;C.P. Kung;T.C. Chang |
| 國立成功大學 |
2007-07-16 |
Layout design for flexible manufacturing systems considering single-loop directional flow patterns
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Yang, Taho; Peters, Brett A.; Tu, Mingan |
| 國立交通大學 |
2014-12-08T15:26:21Z |
Layout design of high-quality SOI varactor
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Chen, HY; Chen, KM; Huang, GW; Huang, CH; Yang, TH; Chang, CY |
| 國立交通大學 |
2014-12-08T15:26:43Z |
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process
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Ker, MD; Chuang, CH; Lo, WY |
| 國立交通大學 |
2014-12-08T15:43:05Z |
Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit
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Ker, MD; Chen, TY |
| 國立臺灣科技大學 |
2003 |
Layout Improvement for the Facility Design of Semiconductor Fabrication
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Chen, J. C. ; Peng, G. M. ; Sun, C. J. ; Wang, J. J. ; Chang, P. F. ; Dai, R. D. |
显示项目 544721-544730 / 2348617 (共234862页)
<< < 54468 54469 54470 54471 54472 54473 54474 54475 54476 54477 > >>
每页显示[10|25|50]项目
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