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显示项目 916691-916715 / 2348419 (共93937页)
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机构 日期 题名 作者
臺大學術典藏 2018-09-10T06:32:26Z VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps RAY-I CHANG;HSIAO, PY;CHANG, RI; CHANG, RI; HSIAO, PY; RAY-I CHANG
臺大學術典藏 2018-09-10T08:34:15Z VLSI design and implementation of density-based spike classification for neuroprosthetic applications Cheng, L.-F.;Chen, T.-C.;Chen, L.-G.; Cheng, L.-F.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN
國立聯合大學 2004 VLSI Design and Implementation of The Re-configurable 2-D Von Neumann Cellular Automata Bases Generator for The Image Processing Applications 陳榮堅, 賴瑞麟
國立交通大學 2014-12-08T15:46:11Z VLSI design for high-speed LZ-based data compression Chen, JM; Wei, CH
國立中山大學 1998-06 VLSI design of A 1.0 GHz 0.6-µm 8-Bit CLA using PLA-styled all-N-transistor Logic C.C. Wang;K.C. Tsai
國立交通大學 2014-12-08T15:27:27Z VLSI design of a priority arbitrator for shared buffer ATM switches Lin, YS; Yang, SC; Fang, SJ; Shung, CB
臺大學術典藏 2018-09-10T04:13:19Z VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems Hsu, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU
國立臺灣大學 2002-08 VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems Hsu, Huai-Yi; Wu, An-Yeu
臺大學術典藏 2003 VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu; Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu
國立臺灣大學 2003 VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu
臺大學術典藏 2019-10-24T07:57:17Z VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems 吳安宇;AN-YEU(ANDY) WU;An-Yeu Wu;Chih-Hsiu Lin;Ching-Hua Wen;Jen-Chih Kuo; Jen-Chih Kuo; Ching-Hua Wen; Chih-Hsiu Lin; An-Yeu Wu; AN-YEU(ANDY) WU; 吳安宇
國立臺灣師範大學 2019-09-03T10:49:33Z VLSI Design of Advanced Encryption Standard 葉幸彰; Hsing-Chang Yeh
國立中山大學 2000-08 VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking Shen-Fu Hsiao;Yor-Chin Tai;Kai-Hsiang Chang
國立中山大學 2000-06 VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking Shen-Fu Hsiao; Yor-Chin Tai; Kai-Hsiang Chang
國立成功大學 2019-01 VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications Shiau;Yeu-Horng;Kuo;Yao-Tsung;Chen;Pei-Yin;Hsu;Feng-Yuan
東方設計學院 2011-02 VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm Kuan,; Ta-Wen; Wang, Jhing-Fa; Wang, Jia-Ching; Lin, Po-Chuan; Gu, Gaung-Hui; 林博川; (東方設計學院電子與資訊系)
國立成功大學 2012-04 VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm Kuan, Ta-Wen; Wang, Jhing-Fa; Wang, Jia-Ching; Lin, Po-Chuan; Gu, Gaung-Hui
國立臺灣大學 1995-05 VLSI design of clustering analyser using systolic arrays Lai, M.F.; Nakano, M.; Wu, Y.P.; Hsieh, C.H.
臺大學術典藏 2004-05 VLSI design of dual-mode Viterbi/turbo decoder for 3GPP Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu
國立臺灣大學 2004-05 VLSI design of dual-mode Viterbi/turbo decoder for 3GPP Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu
元智大學 Feb-15 VLSI Design of FM0/Manchester Encoder with Reuse-Oriented Boolean Simplification Technique for DSRC Applications Yu-Hsuan Lee; Cheng-Wei Pan
義守大學 2001-11 VLSI Design of Inverse-Free Berlekamp-Massey Algorithm for Reed-Solomon Code Truong, T.K. ; Chang, Y.W. ; Jeng, J.H.
元智大學 Jan-16 VLSI Design of Lossless Frame Recompression Using Multi-Orientation Prediction Yu-Hsuan Lee; Yi-Lun You; Yi-Guo Chen
元智大學 2023-08-01 VLSI design of new sorting method implements to the ORBGRAND Szu-Hao Huang; Cheng-Hung Lin
國立成功大學 2023 VLSI Design of Number Theoretic Transform for BGV Fully Homomorphic Encryption Chen, K.-Y.;Shieh, M.-D.

显示项目 916691-916715 / 2348419 (共93937页)
<< < 36663 36664 36665 36666 36667 36668 36669 36670 36671 36672 > >>
每页显示[10|25|50]项目