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教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
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機構 日期 題名 作者
臺大學術典藏 2018-09-10T08:34:18Z Hardware-efficient belief propagation HOMER H. CHEN; LIANG-GEE CHEN; Chen, H.H.; Chen, L.-G.; Liang, C.-K.;Cheng, C.-C.;Lai, Y.-C.;Chen, L.-G.;Chen, H.H.; Liang, C.-K.; Cheng, C.-C.; Lai, Y.-C.
國立交通大學 2014-12-08T15:44:50Z Hardware-efficient DFT designs with cyclic convolution and subexpression sharing Chang, TS; Guo, JI; Jen, CW
國立交通大學 2014-12-08T15:30:54Z Hardware-Efficient EVD Processor Architecture in FastICA for Epileptic Seizure Detection Shih, Yi-Hsin; Chen, Tsan-Jieh; Yang, Chia-Hsiang; Chiueh, Herming
臺大學術典藏 2018-09-10T09:22:19Z Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection Shih, Y.-H.; Chen, T.-J.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG
國立成功大學 2012-05 Hardware-Efficient Filterbank Design for Fast Recursive MDST and IMDST Algorithms Lai, Shin-Chi; Yeh, Yi-Ping; Lei, heau-Fang
國立交通大學 2014-12-08T15:46:06Z Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:43:18Z Hardware-efficient pipelined programmable FIR filter design Chang, TS; Jen, CW
臺大學術典藏 2018-09-10T09:22:24Z Hardware-efficient true motion estimator based on Markov Random Field motion vector correction Chen, F.-C.; Huang, Y.-L.; Chien, S.-Y.; SHAO-YI CHIEN
臺大學術典藏 2020-06-16T06:38:10Z Hardware-Efficient Two-Stage Saliency Detection Wu, S.-Y.;Lin, Y.-S.;Tu, W.-C.;Chien, S.-Y.; Wu, S.-Y.; Lin, Y.-S.; Tu, W.-C.; Chien, S.-Y.; SHAO-YI CHIEN
國立臺灣大學 2008 Hardware-Enhanced Association Rule Mining with Hashing and Pipeling Wen, I.-S.; Huang, J.-W.; Chen, M.-S.
臺大學術典藏 2018-09-10T07:02:38Z Hardware-enhanced association rule mining with hashing and pipelining Wen, Y.-H.; Huang, J.-W.; Chen, M.-S.; MING-SYAN CHEN
大葉大學 2009 Hardware-in-the-Loop Experiments of Vehicle Stability Control for a Brake-by-Wire System Chen, Chih-Keng;Dao, Trung-Kien
大葉大學 2008 Hardware-in-the-Loop Experiments of Vehicle Stability Control for a Brake-by-Wire System Chen, Chih-Keng;Dao, Trung-Kien
大葉大學 2009 Hardware-in-the-Loop Experiments of Vehicle Stability Control system via a hydraulic model Chen, Chih-Keng;Dao, Trung-Kien;Hsieh, Sen-Hsiung
大葉大學 2009 Hardware-in-the-Loop Experiments of Vehicle Stability Control via a Hydraulic Model Chen, Chih-Keng;Dao, Trung-Kien;Hsieh, Sen-Hsiung
臺大學術典藏 2021-10-21T23:27:22Z Hardware-in-the-loop simulation of self-driving electric vehicles by dynamic path planning and model predictive control Chung, Yi; YEE-PIEN YANG
臺大學術典藏 2022-03-22T08:26:06Z Hardware-in-the-loop simulation of self-driving electric vehicles by dynamic path planning and model predictive control Chung Y;Yang Y.-P.; Chung Y; Yang Y.-P.; YEE-PIEN YANG
臺大學術典藏 2022-03-22T08:28:55Z Hardware-in-the-loop simulation of self-driving electric vehicles by dynamic path planning and model predictive control Chung Y;Yang Y.-P.; Chung Y; Yang Y.-P.; YEE-PIEN YANG
臺大學術典藏 2022-03-22T08:28:55Z Hardware-in-the-loop simulation of self-driving electric vehicles by dynamic path planning and model predictive control Chung Y;Yang Y.-P.; Chung Y; Yang Y.-P.; YEE-PIEN YANG
臺大學術典藏 2018-09-10T05:15:51Z Hardware-oriented design for weighted median filters Chen, Chun-Te;Chen, Liang-Gee;Hsiao, Jue-Hsuan; Chen, Chun-Te; Chen, Liang-Gee; Hsiao, Jue-Hsuan; LIANG-GEE CHEN
國立臺灣大學 2008 Hardware-oriented image inpainting for perceptual I-frame error concealment Chen, Ching-Yi; Wu, Guan-Lin; Chien, Shao-Yi
臺大學術典藏 2018-09-10T07:03:43Z Hardware-oriented image inpainting for perceptual I-frame error concealment Chen, Ching-Yi; Wu, Guan-Lin; Chien, Shao-Yi; SHAO-YI CHIEN; Chen, Ching-Yi
國立交通大學 2019-10-05T00:09:44Z HARDWARE-ORIENTED MEMORY-LIMITED ONLINE FASTICA ALGORITHM AND HARDWARE ARCHITECTURE FOR SIGNAL SEPARATION Van, Lan-Da; Lu, Tsung-Che; Jung, Tzyy-Ping; Wang, Jo-Fu
臺大學術典藏 2003-05 Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder Hsu, Chih-Wei; Chang, Yung-Chi; Chao, Wei-Min; Chen, Liang-Gee; Hsu, Chih-Wei; Chang, Yung-Chi; Chao, Wei-Min; Chen, Liang-Gee
國立臺灣大學 2003-05 Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder Hsu, Chih-Wei; Chang, Yung-Chi; Chao, Wei-Min; Chen, Liang-Gee

顯示項目 460901-460925 / 2347236 (共93890頁)
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每頁顯示[10|25|50]項目