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顯示項目 598681-598690 / 2348674 (共234868頁)
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| 國立交通大學 |
2014-12-08T15:35:46Z |
Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications
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Chang, Ming-Hung; Hsieh, Wei-Chih; Wu, Pei-Chen; Chuang, Ching-Te; Chen, Kuan-Neng; Wang, Chen-Chao; Ting, Chun-Yen; Chen, Kua-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Hwang, Wei |
| 國立臺灣科技大學 |
2017 |
Multi-layer age regression for face age estimation
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Ng, C.-C.;Cheng, Y.-T.;Hsu, G.-S.;Yap, M.H. |
| 臺北醫學大學 |
2001 |
Multi-layer Based Hypermedia Integrated Medical Resources—A Live and Interactive Radiology Reporting System
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劉立; Kao-Lun; Wang; L. Liu |
| 國立東華大學 |
2009-10 |
Multi-Layer based Video Inpainting of Occluded Objects
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Chang,I-Cheng; Hsu,Chia-We |
| 國立臺灣科技大學 |
2010 |
Multi-layer bus minimization for SoC
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Chen Y.-S.; Tsai H.-L.; Lo S.-W. |
| 臺大學術典藏 |
2018-09-10T07:35:25Z |
Multi-layer bus optimization for real-time task scheduling with chain-based precedence constraints
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TEI-WEI KUO; Kuo, T.-W.; Lee, D.-N.; Hsiu, P.-C.; Hsiu, P.-C.;Lee, D.-N.;Kuo, T.-W. |
| 臺大學術典藏 |
2020-05-04T08:06:59Z |
Multi-layer Bus Optimization for Real-Time Task Scheduling with Chain-Based Precedence Constraints.
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Hsiu, Pi-Cheng;Lee, Der-Nien;Kuo, Tei-Wei; Hsiu, Pi-Cheng; Lee, Der-Nien; Kuo, Tei-Wei; TEI-WEI KUO |
| 臺大學術典藏 |
2022-09-21T23:30:16Z |
Multi-Layer Chips on Wafer Stacking Technologies with Carbon Nano-Tubes as Through-Silicon Vias and it's potential applications for Power-Via technologies
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Liao, Bo Zhou; Chen, Liang Hsi; Chen, Kai Cheng; Lin, Hong Yi; Tsai, Yi Ting; Chen, Ting Wei; Chan, Yi Cheng; Lee, Min Hung; MING-HAN LIAO |
| 元智大學 |
2004-05 |
Multi-layer Constrained Via Minimization with Conjugate Conflict Cuntinuation Graphs
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林榮彬; 陳淑瑜 |
| 國立成功大學 |
2019 |
Multi-layer elemental 2D materials: Antimonene, germanene and stanene grown directly on molybdenum disulfides
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Chen, K.-C.;Lee, Lee L.-M.;Chen, H.-A.;Sun, H.;Wu, C.-L.;Chen, H.-A.;Lin, K.-B.;Tseng, Y.-C.;Kaun, C.-C.;Pao, C.-W.;Lin, S.-Y. |
顯示項目 598681-598690 / 2348674 (共234868頁)
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每頁顯示[10|25|50]項目
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