| 國立臺灣海洋大學 |
2013 |
VLDLR在粒線體功能缺損誘發人類肝癌細胞HepG2惡化之角色
|
Meng-Hsuan Hu; 胡孟宣 |
| 臺大學術典藏 |
2005 |
VLE calculation for non-polar fluid mixtures and polymer solutions using a SAFT-VR type equation of state
|
Chen, Yan-Ping; Tsai, Jung-Chin; Tsai, Jung-Chin; Chen, Yan-Ping |
| 國立臺灣大學 |
2005 |
VLE calculation for non-polar fluid mixtures and polymer solutions using a SAFT-VR type equation of state
|
Tsai, Jung-Chin; Chen, Yan-Ping |
| 國立臺灣大學 |
1997 |
VLE calculations by applying a modified perturbed hard sphere EOS
|
Yu, Min-Lon; Chen, Yan-Ping |
| 國立臺灣大學 |
1982 |
VLF-Wave-Induced Precipitation of Quasi-Relativistic Particles in the Magnetosphere
|
張宏鈞; Inan, U. S.; Bell, T. F.; Chang, Hung-Chun; Inan, U. S.; Bell, T. F. |
| 國立中山大學 |
2003-06-25 |
VLIW DSP架構之增進指令並行度之向量化運算機制
|
楊得鑫 |
| 中華大學 |
2004 |
VLIW Processor with Embedded Watchdog Processor for Control Flow Error Detection
|
陳永源; Chen, Yung-Yuan |
| 淡江大學 |
2024-07-31T04:08:27Z |
Vloggers and consumer choices in the hotel and hospitality sector: The double-edged sword of discounts
|
Ni, Yensen |
| 國立成功大學 |
2005-04 |
VLSI architectural design tradeoffs for sliding-window Log-MAP decoders
|
Wu, Chien-Ming; Shieh, Ming-Der; Wu, Chien-Hsing; Hwang, Yin-Tsung; Chen, Jun-Hong |
| 國立成功大學 |
2002-08 |
VLSI architecture and implementation for speech recognizer based on discriminative Bayesian neural network
|
Wang, Jhing-Fa; Wang, Jia-Ching; Suen, An-Nan; Wu, Chung-Hsien; Li, Fan-Min |
| 臺大學術典藏 |
2018-09-10T04:07:51Z |
VLSI architecture design and implementation for TWOFISH block cipher
|
Lai, Y.-K.; Chen, L.-G.; Lai, J.-Y.; Parng, T.-M.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2001-07-31 |
VLSI Architecture Design and Implementation of IF and Baseband Analog Front End for Digital Multimedia Wireless Receiver (II)
|
汪重光 |
| 亞洲大學 |
2002-05-16 |
VLSI ARCHITECTURE DESIGN FOR TWOFISH BLOCK CIPHER
|
Li-Chung Chang ;Yeong-Kang Lai; Liang-Gee Chen;Jian-Yi La;Tai-Ming Parng |
| 中國文化大學 |
1997-06 |
VLSI Architecture Design of a High Performance Clustering Analyzer
|
賴茂富 |
| 元智大學 |
Dec-15 |
VLSI Architecture Design of FM0/Manchester Codec with 100% Hardware Utilization Rate for DSRC-Based Sensor Nodes in ITS Applications
|
Yu-Hsuan Lee; Cheng-Wei Pan; Fang-Hsu Tsai |
| 國立臺灣大學 |
2008 |
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
|
Chen, Yi-Hau; Chen, Tung-Chien; Chien, Shao-Yi; Huang, Yu-Wen; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T14:57:57Z |
VLSI architecture design of guided filter for 30 frames/s full-HD Video
|
Kao, C.-C.;Lai, J.-H.;Chien, S.-Y.; Kao, C.-C.; Lai, J.-H.; Chien, S.-Y.; SHAO-YI CHIEN |
| 臺大學術典藏 |
2020-06-16T06:38:08Z |
VLSI architecture design of layer-based bilateral and median filtering for 4k2k videos at 30fps
|
Tai, M.-Y.;Tu, W.-C.;Chien, S.-Y.; Tai, M.-Y.; Tu, W.-C.; Chien, S.-Y.; SHAO-YI CHIEN |
| 義守大學 |
2003-10 |
VLSI architecture design of modified Euclidean algorithm for Reed-Solomon code
|
Y.W. Chang;J.H. Jeng;T.K. Truong |
| 國立交通大學 |
2014-12-08T15:25:57Z |
VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders
|
Wang, YY; Peng, YT; Tsai, CJ |
| 臺大學術典藏 |
2018-09-10T04:07:51Z |
VLSI architecture design of MPEG-4 shape coding
|
Chang, H.-C.; Chang, Y.-C.; Wang, Y.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2002 |
VLSI architecture design of MPEG-4 shape coding
|
Chang, Hao-Chieh; Chang, Yung-Chi; Wang, Yi-Chu; Chao, Wei-Ming; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T07:26:43Z |
VLSI architecture design of VLC encoder for high data rate video/image coding
|
Chang, Hao-Chieh; Chen, Liang-Gee; Chang, Yung-Chi; Huang, Sheng-Chieh; LIANG-GEE CHEN |
| 臺大學術典藏 |
2003-08 |
VLSI architecture for discrete wavelet transform based on B-spline factorization
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2003-08 |
VLSI architecture for discrete wavelet transform based on B-spline factorization
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:42Z |
VLSI architecture for discrete wavelet transform based on B-spline factorization
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:44Z |
VLSI architecture for fifting-based shape-adaptive discrete wavelet transform with odd-symmetric filters
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2005 |
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T05:15:44Z |
VLSI architecture for forward discrete wavelet transform based on B-spline factorization
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2005 |
VLSI Architecture for Lifting-based Shape-Adaptive Discrete Wavelet Transform with Odd-symmetric Filters
|
Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立成功大學 |
2018 |
VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation
|
Juang, W.-H.;Lai, S.-C.;Luo, C.-H.;Lee, S.-Y. |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
VLSI architecture for radix-2k Viterbi decoding with transpose algorithm
|
Lee, Wen-Ta;Chen, Thou-Ho;Chen, Liang-Gee; Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee; LIANG-GEE CHEN |
| 國立交通大學 |
2014-12-08T15:27:25Z |
VLSI Architecture for Real-Time HD1080p View Synthesis Engine
|
Horng, Ying-Rung; Tseng, Yu-Cheng; Chang, Tian-Sheuan |
| 國立交通大學 |
2014-12-08T15:05:45Z |
VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design
|
Van, Lan-Da; Lin, Chin-Teng; Yu, Yuan-Chu |
| 義守大學 |
2009-07 |
VLSI Architecture of Euclideanized BM Algorithm for Reed-Solomon Code
|
Huang-Chi Chen;Yu-Wen Chang;Rey-Chue Hwang |
| 國立交通大學 |
2017-04-21T06:49:35Z |
VLSI Architecture of Leading Eigenvector Generation for On-chip Principal Component Analysis Spike Sorting System
|
Chen, Tung-Chien; Liu, Wentai; Chen, Liang-Gee |
| 淡江大學 |
2005 |
VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications
|
Chiang, Jen-Shiun; Hsia, Chih-Hsien; Chen, Hsin-Jung; Lo, Te-Jung |
| 義守大學 |
2003-10 |
VLSI architecture of modified Euclidean algorithm for Reed-Solomon code
|
Y.W. Chang;T.K. Truong;J.H. Jeng |
| 國立成功大學 |
2020 |
VLSI architecture of polynomial multiplication for BGV fully homomorphic encryption
|
Hsu, Hsu H.-J.;Shieh, M.-D. |
| 國立成功大學 |
2022 |
VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic
|
Teng;You-Tun;Chin;Wen-Long;Chang;Deng-Kai;Chen;Pei-Yin;Chen;Pin-Wei |
| 中華大學 |
2006 |
VLSI Architectures for 2-D Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Architectures for 2-D Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters
|
謝曜式; Shieh, Yaw-Shih |
| 中原大學 |
2001-10-11 |
VLSI CAD中一些最佳化問題之研究
|
林佑政; Yu-Chung Lin |
| 中原大學 |
1989 |
VLSI CAD數位語音系統之設計
|
王如生; WANG, RU-SHENG |
| 國立交通大學 |
2014-12-08T15:03:00Z |
VLSI cell placement on arbitrarily-shaped rectilinear regions using neural networks with calibration nodes
|
Chang, RI; Hsiao, PY |
| 臺大學術典藏 |
2018-09-10T05:24:37Z |
VLSI cell placement on arbitrarily-shaped rectilinear regions using neural networks with calibration nodes
|
RAY-I CHANG;HSIAO, PY;CHANG, RI; CHANG, RI; HSIAO, PY; RAY-I CHANG |
| 國立交通大學 |
2014-12-08T15:01:53Z |
VLSI cell placement on arbitrarily-shaped rectilinear regions using neural networks with calibration nodes - Comments
|
Huang, KY |
| 國立中山大學 |
2001-09 |
VLSI circuit design of 16-Mbps IrDA VFIR transceivers
|
C.C. Wang;C.W. Chen;Y.L. Huang |
| 國立交通大學 |
2014-12-08T15:01:29Z |
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
|
Chang, RI; Hsiao, PY |
| 國立交通大學 |
2019-04-02T05:59:32Z |
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
|
Chang, RI; Hsiao, PY |
