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顯示項目 916656-916665 / 2348419 (共234842頁)
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| 國立臺灣大學 |
2008 |
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
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Chen, Yi-Hau; Chen, Tung-Chien; Chien, Shao-Yi; Huang, Yu-Wen; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T14:57:57Z |
VLSI architecture design of guided filter for 30 frames/s full-HD Video
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Kao, C.-C.;Lai, J.-H.;Chien, S.-Y.; Kao, C.-C.; Lai, J.-H.; Chien, S.-Y.; SHAO-YI CHIEN |
| 臺大學術典藏 |
2020-06-16T06:38:08Z |
VLSI architecture design of layer-based bilateral and median filtering for 4k2k videos at 30fps
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Tai, M.-Y.;Tu, W.-C.;Chien, S.-Y.; Tai, M.-Y.; Tu, W.-C.; Chien, S.-Y.; SHAO-YI CHIEN |
| 義守大學 |
2003-10 |
VLSI architecture design of modified Euclidean algorithm for Reed-Solomon code
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Y.W. Chang;J.H. Jeng;T.K. Truong |
| 國立交通大學 |
2014-12-08T15:25:57Z |
VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders
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Wang, YY; Peng, YT; Tsai, CJ |
| 臺大學術典藏 |
2018-09-10T04:07:51Z |
VLSI architecture design of MPEG-4 shape coding
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Chang, H.-C.; Chang, Y.-C.; Wang, Y.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2002 |
VLSI architecture design of MPEG-4 shape coding
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Chang, Hao-Chieh; Chang, Yung-Chi; Wang, Yi-Chu; Chao, Wei-Ming; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T07:26:43Z |
VLSI architecture design of VLC encoder for high data rate video/image coding
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Chang, Hao-Chieh; Chen, Liang-Gee; Chang, Yung-Chi; Huang, Sheng-Chieh; LIANG-GEE CHEN |
| 國立臺灣大學 |
2003-08 |
VLSI architecture for discrete wavelet transform based on B-spline factorization
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Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:42Z |
VLSI architecture for discrete wavelet transform based on B-spline factorization
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Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
顯示項目 916656-916665 / 2348419 (共234842頁)
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