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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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顯示項目 256321-256330 / 2346275 (共234628頁)
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| 義守大學 |
1999-07 |
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS
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Ker, Ming-Dou ; Wang, Chang-Tzu |
| 國立成功大學 |
2021-06-01 |
Circuit system and circuit control method applied to motor drive
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Tsai, Mi-Ching;Pai, Fu-Sheng;Hsieh, Min-Fu;Shih, Kai-Jung;Wu, Zheng-Xuan; 蔡明祺 |
| 國立臺灣科技大學 |
2007-03 |
Circuit Techniques for CMOS Divide-By-Four Frequency Divider
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Jang, S.-L.;Chuang, Y.-H.;Lee, S.-H.;Chao, J.-J. |
| 國立屏東大學 |
2007 |
Circuit Tolerance Design Using an Improved Immune Algorithm
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蔡進聰;J.T.Tsai;W.H.Ho;J.H.Chou;T.K.Liu |
| 國立中山大學 |
1992-05 |
Circuit Verification Using a Theorem Prover
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S.J. Lee;W.J. Lin |
| 國立交通大學 |
2019-09-02T07:46:21Z |
Circuit-based logical layer 2 bridging in software-defined data center networking
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Wang, Yao-Chun; Lin, Ying-Dar |
| 國立交通大學 |
2015-12-02T02:59:16Z |
Circuit-Simulation-Based Multi-Objective Evolutionary Algorithm for Design Optimization of a-Si:H TFTs Gate Driver Circuits Under Multilevel Clock Driving
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Hung, Sheng-Chin; Chiang, Chien-Hsueh; Li, Yiming |
| 國立交通大學 |
2019-04-02T06:04:33Z |
Circuit-Simulation-Based Multi-objective Evolutionary Algorithm with Multi-Level Clock Driving Technique for a-Si:H TFTs Gate Driver Circuit Design Optimization
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Hung, Sheng-Chin; Chen, Chieh-Yang; Chiang, Chien-Hsueh; Li, Yiming |
| 國立交通大學 |
2014-12-08T15:43:19Z |
Circuit-switched broadcasting in multi-port multi-dimensional torus networks
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Wang, SY; Tseng, YC; Ni, SY; Sheu, JP |
| 義守大學 |
2001-11 |
Circuit-switched broadcasting in multi-port multi-dimensional torus networks
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San-Yuan Wang;Yu-Chee Tseng;Sze-Yao Ni;Jang-Ping Sheu |
顯示項目 256321-256330 / 2346275 (共234628頁)
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每頁顯示[10|25|50]項目
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