| 國立臺灣大學 |
2008 |
Hardware architecture design and implementation of ray-triangle intersection with bounding volume hierarchies
|
Chang, Chen-Haur; Lee, Chuan-Yiu; Chien, Shao-Yi |
| 臺大學術典藏 |
2004-05 |
Hardware architecture design for H.264/AVC intra frame coder
|
Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee; Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Hardware architecture design for H.264/AVC intra frame coder
|
Huang, Yu-Wen; Hsieh, Bing-Yu; Chen, Tung-Chien; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:21Z |
Hardware architecture design for H.264/AVC intra frame coder
|
Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2003-05 |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Hsieh, Bing-Yu; Chen, Liang-Gee; Wang, Tu-Chih; Huang, Yu-Wen; Wang, Tu-Chih; Hsieh, Bing-Yu; Chen, Liang-Gee; Huang, Yu-Wen |
| 國立臺灣大學 |
2003-05 |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Huang, Yu-Wen; Wang, Tu-Chih; Hsieh, Bing-Yu; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Huang, Y.-W.; Wang, T.-C.; Hsieh, B.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2004-08 |
Hardware architecture design for visual processing: present and future
|
Tseng, Po-Chih; Chen, Liang-Gee; Tseng, Po-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-08 |
Hardware architecture design for visual processing: present and future
|
Tseng, Po-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:20Z |
Hardware architecture design for visual processing: Present and future
|
Tseng, P.-C.; Chen, L.-G.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2006-01 |
Hardware architecture design of an H.264/AVC video codec
|
Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee; Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee |
| 國立臺灣大學 |
2006-01 |
Hardware architecture design of an H.264/AVC video codec
|
Chen, Tung-Chien; Lian, Chung-Jr; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T05:50:30Z |
Hardware architecture design of an H.264/AVC video codec
|
Chen, T.-C.; Lian Jr.; C.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2011 |
Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation
|
Hsu, Kung-Yen; Chien, Shao-Yi |
| 臺大學術典藏 |
2018-09-10T08:42:33Z |
Hardware architecture design of frame rate up-conversion for high definition videos with global motion estimation and compensation
|
Hsu, Kung-Yen;Chien, Shao-Yi; Hsu, Kung-Yen; Chien, Shao-Yi; SHAO-YI CHIEN |
| 臺大學術典藏 |
2018-09-10T09:22:24Z |
Hardware architecture design of hybrid distributed video coding with frame level coding mode selection
|
Chiu, C.-C.; Wu, H.-F.; Chien, S.-Y.; Lee, C.-H.; Somayazulu, V.S.; Chen, Y.-K.; SHAO-YI CHIEN |
| 國立臺灣大學 |
2005-08 |
Hardware architecture design of video compression for multimedia communication systems
|
Chien, Shao-Yi; Huang, Yu-Wen; Chen, Ching-Yeh; Chen, Homer H.; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Hardware architecture design of video compression for multimedia communication systems
|
Chen, Liang-Gee; Chen, Homer H.; Chen, Ching-Yeh; Huang, Yu-Wen; LIANG-GEE CHEN; Chien, Shao-Yi; Chien, Shao-Yi; LIANG-GEE CHEN |
| 臺大學術典藏 |
2007-04-19T04:02:59Z |
Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile
|
Chen, Liang-Gee;Chien, Shao-Yi;Huang, Yu-Wen;Chen, Ching-Yeh;Chao, Wei-Min; Chen, Ching-Yeh; Chien, Shao-Yi; Chao, Wei-Min; Huang, Yu-Wen; Chen, Liang-Gee |
| 國立臺灣大學 |
2004-05 |
Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile
|
Chen, Ching-Yeh; Chien, Shao-Yi; Chao, Wei-Min; Huang, Yu-Wen; Chen, Liang-Gee |
| 臺大學術典藏 |
2018-09-10T04:47:19Z |
Hardware architecture for global motion estimation for MPEG-4 advanced simple profile
|
Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立交通大學 |
2014-12-08T15:09:16Z |
Hardware Architecture for High-Performance Regular Expression Matching
|
Lee, Tsern-Huei |
| 中華大學 |
2011 |
Hardware Architecture of Real-Time Stereoscopic Image Generation from Depth Map
|
鄭芳炫; Cheng, Fang Hsuan |
| 國立臺灣大學 |
2007 |
Hardware Architecture to Realize Multi-layer Image Processing in Real-time
|
Fu, Li-Chen; Lu Chieh-Lun |
| 臺大學術典藏 |
2018-09-10T06:30:49Z |
Hardware architecture to realize multi-layer image processing in real-time
|
Fu, Li-Chen; Lu Chieh-Lun; LI-CHEN FU |
| 亞洲大學 |
2007-12-20 |
Hardware Context Switching Methodology for Dynamically Partially Reconfigurable Systems
|
Trong-Yen Lee; Che-Cheng Hu; Li-Wen Lai; Chia-Chun Tsai and Rong-Shue Hsiao |
| 國立成功大學 |
2016-06 |
Hardware Design and Implementation for Empirical Mode Decomposition
|
Chen, Pei-Yin; Lai, Yen-Chen; Zheng, Ju-Yang |
| 國立臺灣科技大學 |
2017 |
Hardware design for statistical network traffic classifiers
|
Lu, C.-N;Lai, Y.-C;Huang, C.-Y;Lin, Y.-D. |
| 國立交通大學 |
2018-08-21T05:56:54Z |
Hardware Design for Statistical Network Traffic Classifiers
|
Lu, Chun-Nan; Lai, Yuan-Cheng; Huang, Chun-Ying; Lin, Ying-Dar |
| 國立彰化師範大學 |
1995 |
Hardware Design of A Real-Time Petri Net Model for Real-Time Tasks
|
黃其泮;何正信 |
| 國立成功大學 |
2018-11 |
Hardware Design of an Energy-Efficient High-Throughput Median Filter
|
Lin;Shih-Hsiang;Chen;Pei-Yin;Lin;Chang-Hsing |
| 國立臺灣科技大學 |
2010 |
Hardware design of features extraction using wavelet packet method for intelligent diagnostic system
|
Huang C.-C.; Huang C.-H.; Tsao Y.-M.; Huang S.-C.; Huang H.-L. |
| 國立成功大學 |
2017-08-1 |
Hardware Design of Low-Power High-Throughput Sorting Unit
|
Lin;Shih-Hsiang;Chen;Pei-Yin;Lin;Yu-Ning |
| 國立臺灣大學 |
1997-06 |
Hardware efficient design of filter banks for video coding
|
Wu, Po-Cheng; Chen, Liang-Gee; Liu, Yuan-Chen; Lai, Yeong-Kang |
| 臺大學術典藏 |
2018-09-10T06:20:27Z |
Hardware efficient design of filter banks for video coding
|
Wu, Po-Cheng; Chen, Liang-Gee; Liu, Yuan-Chen; Lai, Yeong-Kang; LIANG-GEE CHEN |
| 國立交通大學 |
2014-12-08T15:03:36Z |
Hardware efficient skip mode detection for H.264/AVC
|
Lin, Chia-Chun; Lin, Yu-Kun; Chang, Tian-Sheuan |
| 國立交通大學 |
2014-12-08T15:27:17Z |
Hardware efficient transform designs with cyclic formulation and subexpression sharing
|
Chang, TS; Jen, CW |
| 臺大學術典藏 |
2018-09-10T05:57:28Z |
Hardware enhanced mining for association rules
|
Liu, W.-C.; Liu, K.-H.; Chen, M.-S.; MING-SYAN CHEN |
| 國立臺灣大學 |
2010 |
Hardware Equivalence and Property Verification
|
Jiang, Jie-Hong R.; Villa, Tiziano |
| 臺大學術典藏 |
2018-09-10T08:19:13Z |
Hardware Equivalence and Property Verification
|
Jie-Hong R. Jiang;Tiziano Villa; Jie-Hong R. Jiang; Tiziano Villa; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:11Z |
Hardware Equivalence and Property Verification.
|
Jiang, Jie-Hong Roland;Villa, Tiziano;Crama, Yves;Hammer, Peter L.; Jiang, Jie-Hong Roland; Villa, Tiziano; Crama, Yves; Hammer, Peter L.; JIE-HONG JIANG |
| 元智大學 |
2020/12/3 |
Hardware for Controlling a Dynamic Lighting System
|
Apoorv Mahesh Chaudhari; Chiung Reng Tai; Nafia AL-Mutawaly; Hsu Y.-L.; Jonathon David White |
| 國立成功大學 |
2008-04 |
Hardware implementation for a genetic algorithm
|
Chen, Pei-Yin; Chen, Ren-Der; Chang, Yu-Pin; Shieh, Leang-San; Malki, Heidar A. |
| 國立彰化師範大學 |
2008-04 |
Hardware Implementation for a Genetic Algorithm
|
Chen, Pei-Yin; Chen, Ren-Der; Chang, Yu-Pin; Shieh, Leang-San; Malki, Heidar A. |
| 國立臺灣大學 |
2004-05-31 |
Hardware Implementation Issues on Viterbi Decoder
|
Wu, Meng-Hau |
| 國立成功大學 |
2017 |
Hardware implementation of a distributed pv system based on the central operation of the MPPT algorithm
|
Chao, R.-M.;Jhang, Jhang J.-C.;Wang, I.-K.;Hsu, S.-C. |
| 國立成功大學 |
2013-08 |
Hardware Implementation of a Fast and Efficient Haze Removal Method
|
Shiau, Yeu-Horng; Yang, Hung-Yu; Chen, Pei-Yin; Chuang, Ya-Zhu |
| 中華大學 |
2007 |
Hardware Implementation of a High-Speed (32, 24, 4) RS Decoder
|
陳棟洲; Chen, Tung-Chou |
| 國立彰化師範大學 |
2007-12 |
Hardware Implementation of a High-Speed (32, 24, 4) RS Decoder
|
Chen, Tung-Chou; Tasi, Ming-Hsi |
| 國立臺灣海洋大學 |
2008-06-18 |
Hardware Implementation of a Hybrid Intelligent Controller for a Twin Rotor MIMO System
|
Jih-Gau Juang;Wen-Kai Liu |
