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Institution Date Title Author
國立臺灣大學 2004-05-31 Hardware Implementation Issues on Viterbi Decoder Wu, Meng-Hau
國立成功大學 2017 Hardware implementation of a distributed pv system based on the central operation of the MPPT algorithm Chao, R.-M.;Jhang, Jhang J.-C.;Wang, I.-K.;Hsu, S.-C.
國立成功大學 2013-08 Hardware Implementation of a Fast and Efficient Haze Removal Method Shiau, Yeu-Horng; Yang, Hung-Yu; Chen, Pei-Yin; Chuang, Ya-Zhu
中華大學 2007 Hardware Implementation of a High-Speed (32, 24, 4) RS Decoder 陳棟洲; Chen, Tung-Chou
國立彰化師範大學 2007-12 Hardware Implementation of a High-Speed (32, 24, 4) RS Decoder Chen, Tung-Chou; Tasi, Ming-Hsi
國立臺灣海洋大學 2008-06-18 Hardware Implementation of a Hybrid Intelligent Controller for a Twin Rotor MIMO System Jih-Gau Juang;Wen-Kai Liu
國立彰化師範大學 2008-05 Hardware Implementation of a MAC Module for Wireless Communication Systems Chen, Tung-Chou; Kuan, Po-Tse; Hung, Shin-Chi
臺大學術典藏 2018-09-10T15:23:06Z Hardware implementation of a real-time distributed video decoder Yang, H.-P.;Ho, M.-H.;Hsieh, H.-C.;Cheng, P.-H.;Chen, S.-J.; Yang, H.-P.; Ho, M.-H.; Hsieh, H.-C.; Cheng, P.-H.; Chen, S.-J.; SAO-JIE CHEN
國立臺灣海洋大學 2008-07-06 Hardware Implementation of Aircraft Landing Controller by Evolutionary Computation and DSP Jih-Gau Juang;Hou-Kai Chiou
淡江大學 2016/9/23 Hardware implementation of an adaptive fuzzy wavelet neural network control for voice coil motors Hsu, Chun-Fei; Wong, Kai-Yi; Su, Chien-Min; Lee, Tsu-Tian
淡江大學 2016/09/23 Hardware implementation of an adaptive fuzzy wavelet neural network control for voice coil motors Hsu, Chun-Fei;Lee, Tsu-Tian
國立成功大學 2018-01 Hardware Implementation of an Image Interpolation Method with Controllable Sharpness Chen;Pei-Yin;Lin;Shih-Hsiang;Chen;Po-Chun
淡江大學 2006-12 Hardware Implementation of AWGN Channel Module Wu, Rong-hou; Lee, Yang-han; Tseng, Hsien-wei; Jan, Yih-guang; Tseng, Wei-chieh; Chung, Ming-hsueh; Tseng, Chih-hsiang
國立彰化師範大學 2006-09 Hardware Implementation of Discrete Wavelet Transform for Power Transient Signal Detection Xi-Long Yang; Chau-Shing Wang; Wen-Ren Yang
中華大學 2005 Hardware Implementation of Fast 3-D Rotation Using Double Rotation CORDIC Algorithm in Graphic Engine 宋志雲; Sung, Tze-Yun
中華大學 2005 Hardware Implementation of Fast 3-D Rotation Using Double Rotation CORDIC Algorithm in Graphic Engine 謝曜式; Shieh, Yaw-Shih
中華大學 2005 Hardware Implementation of Fast 3-D Rotation Using Double Rotation CORDIC Algorithm in Graphic Engine 林國珍; Lin, Kuo-Jen
中華大學 2005 Hardware Implementation of High-Throughput 3-D Rotation for Graphic Engine Using Double Rotation CORDIC Algorithm 宋志雲; Sung, Tze-Yun
國立成功大學 2023 Hardware Implementation of High-Throughput S-Box in AES for Information Security Lin;Shih-Hsiang;Lee;Jun-Yi;Chuang;Chia-Chou;Lee;Narn-Yih;Chen;Pei-Yin;Chin;Wen-Long
國立成功大學 2017 Hardware implementation of local mean decomposition Chen, P.-Y.;Lai, Y.-C.;Lai, P.-H.
國立成功大學 2017-01 Hardware Implementation of Local Mean Decomposition Chen;Pei-Yin;Lai;Yen-Chen;Lai;Ping-Hsuan
臺大學術典藏 2021-09-02T00:04:17Z Hardware implementation of physically unclonable function (puf) in perpendicular STT MRAM Wang D.Y;Hsin Y.C;Lee K.Y;Chen G.L;Yang S.Y;Lee H.H;Chang Y.J;Wang I.J;Kuo Y.C;Chen Y.S;Wang P.H;Wu C.I;Tang D.D.; Wang D.Y; CHIH-I WU et al.
臺大學術典藏 2018-09-10T09:25:45Z Hardware Implementation of Pixel Detection in Gray-Scale Holographic Data Storage Systems C. Y. Chen;T. D. Chiueh; C. Y. Chen; T. D. Chiueh; TZI-DAR CHIUEH
淡江大學 2005-12 Hardware Implementation of QoS Scheduling for WiMAX System by Using Genetic Algorithm 李揚漢; 詹益光
義守大學 2010-05 Hardware Implementation of RFID Mutual Authentication Protocol Yu-Jung Huang;Ching-Chien Yuan;Ming-Kun Chen;Wei-Cheng Lin;Hsien-Chiao Teng
臺大學術典藏 2003-09 Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee; Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
國立臺灣大學 2003-09 Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank Huang, Chao-Tsung; Tseng, Po-Chih; Chen, Liang-Gee
臺大學術典藏 2018-09-10T04:27:46Z Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN
義守大學 2010-11 Hardware implementation of triangulation method based on CORDIC algorithm Yen-Chang Huang;Chien-Chang Lai;Yu-Jung Huang
中華大學 2004 Hardware Implementation of Viterbi Decoder for WLAN 802.11a 陳棟洲; Chen, Tung-Chou
臺大學術典藏 2005-12 Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264 Chen, Yu-Han; Chen, Tung-Chien; Chen, Liang-Gee; Chen, Yu-Han; Chen, Tung-Chien; Chen, Liang-Gee
國立臺灣大學 2005-12 Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264 Chen, Yu-Han; Chen, Tung-Chien; Chen, Liang-Gee
臺大學術典藏 2018-09-10T05:15:47Z Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264 Chen, Y.-H.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN
臺大學術典藏 2003-07 Hardware oriented rate control algorithm and implementation for realtime video coding Fang, Hung-Chi; Wang, Tu-Chih; Chang, Yu-Wei; Chen, Liang-Gee; Fang, Hung-Chi; Wang, Tu-Chih; Chang, Yu-Wei; Chen, Liang-Gee
國立臺灣大學 2003-07 Hardware oriented rate control algorithm and implementation for realtime video coding Fang, Hung-Chi; Wang, Tu-Chih; Chang, Yu-Wei; Chen, Liang-Gee
臺大學術典藏 2018-09-10T04:27:46Z Hardware oriented rate control algorithm and implementation for realtime video coding Fang, H.-C.; Wang, T.-C.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN
國立中山大學 1999-11 Hardware realization of a bit-serial 16-bit multiplier using low-power high-speed FPGA logic module for DSP applications C.C. Wang;C.J. Huang;H.L. Wu;H.M. Yang
國立中山大學 1996-05 Hardware realization of multi-valued exponential bidirectional associative memory using current-mode circuits C.C. Wang;Y.C. Chen
國立臺灣科技大學 2012 Hardware resource manager for reconfiguration system Lin, C.-T.;Horng, S.-J.;Huang, Y.-L.
國立交通大學 2014-12-08T15:27:49Z HARDWARE SHARING IN TREE-STRUCTURE QMF BANKS LEE, HR; JEN, CW
國立臺灣科技大學 2009-04 Hardware Simplification to the Delta Path in a MASH 111 Delta–Sigma Modulator Chia-Yu Yao;Chih-Chun Hsieh
國立臺灣大學 2009 HARDWARE SOFTWARE CO-DESIGN OF A MULTIMEDIA SOC PLATFORM Chen, Sao-Jie; Lin, Guang-Huei; Hsiung, Pao-Ann; Hu, Yu–Hen
臺大學術典藏 2018-09-10T07:36:33Z Hardware software co-design of a multimedia SOC platform Hu, Yu-Hen;Hsiung, Pao-Ann;Lin, Guang-Huei;Chen, Sao-Jie; Hu, Yu-Hen; Hsiung, Pao-Ann; Lin, Guang-Huei; Chen, Sao-Jie; Chen, Sao-Jie
臺大學術典藏 1993-10 Hardware verification using symbolic state transition graphs Chen, Pin-Hong; Shyu, Jyuo-Min; Chen, Liang-Gee; Chen, Pin-hong; Shyu, Jyuo-Min; Chen, Liang-Gee
國立臺灣大學 1993-10 Hardware verification using symbolic state transition graphs Chen, Pin-hong; Shyu, Jyuo-Min; Chen, Liang-Gee
臺大學術典藏 2018-09-10T04:27:49Z Hardware verification using symbolic state transition graphs Chen, Pinhong; Shyu, Jyuo-Min; Chen, Liang-Gee; LIANG-GEE CHEN
臺大學術典藏 2020-06-11T06:29:41Z Hardware Verification Using Symbolic State Transition Graphs. Chen, Pinhong;Shyu, Jyuo-Min;Chen, Liang-Gee; Chen, Pinhong; Shyu, Jyuo-Min; Chen, Liang-Gee; LIANG-GEE CHEN
臺大學術典藏 2021-09-21T23:19:35Z Hardware- And Memory-Efficient Architecture for Disparity Estimation of Large Label Counts Wu, Sih Sian; Chen, Hon Hui; LIANG-GEE CHEN
臺大學術典藏 2020-05-04T08:04:29Z Hardware-accelerated cache simulation for multicore by FPGA Hung, S.-H.; Ho, Y.-M.; Yeh, C.-W.; Cheng-Yueh, Lee, C.-P.; SHIH-HAO HUNG
臺大學術典藏 2018 Hardware-accelerated cache simulation for multicore by FPGA. SHIH-HAO HUNG; Lee, Chen-Pang; Liu, Cheng-Yueh; Yeh, Chih Wei; Ho, Yi-Mo; Hung, Shih-Hao

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