English  |  正體中文  |  简体中文  |  0  
???header.visitor??? :  52538112    ???header.onlineuser??? :  769
???header.sponsordeclaration???
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
???ui.leftmenu.abouttair???

???ui.leftmenu.bartitle???

???index.news???

???ui.leftmenu.copyrighttitle???

???ui.leftmenu.link???

???jsp.browse.items-by-title.jump??? [ ???jsp.browse.general.jump2chinese??? ] [ ???jsp.browse.general.jump2numbers??? ] [ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z ]
???jsp.browse.items-by-title.enter???   

Showing items 544726-544750 of 2348570  (93943 Page(s) Totally)
<< < 21785 21786 21787 21788 21789 21790 21791 21792 21793 21794 > >>
View [10|25|50] records per page

Institution Date Title Author
國立臺灣科技大學 2003 Layout Improvement for the Facility Design of Semiconductor Fabrication Chen, J. C. ; Peng, G. M. ; Sun, C. J. ; Wang, J. J. ; Chang, P. F. ; Dai, R. D.
中原大學 2003-03 Layout Improvement for the Facility Design of Semiconductor Fabrication J. C. Chen;G. M. Peng;C. J. Sun;J. J. Wang;P. F. Chang;R. D. Dai;
國立臺灣科技大學 2004 Layout Improvement for Wafer Fabrication Plants Chen, J. C. ; Yang, R. T. ; Peng, K. M. ; Wang, C. C.
中原大學 2004-03 Layout Improvement for Wafer Fabrication Plants J. C. Chen;R. T. Yang;K. M. Peng;C. C. Wang;
臺大學術典藏 2022-09-21T23:30:15Z Layout of 1.50-inch, 3207-ppi oled display with oslsi/silsi structure capable of division driving fabricated through vlsi process with side-by-side patterning by photolithography Saito, Toshihiko; Mizuguchi, Toshiki; Okamoto, Yuki; Ito, Minato; Toyotaka, Kouhei; Kozuma, Munehiro; Matsuzaki, Takanori; Kobayashi, Hidetomo; Onuki, Tatsuya; Hiura, Yoshikazu; Hodo, Ryota; Sasagawa, Shinya; Kunitake, Hitoshi; Nakamura, Daiki; Sato, Hitomi; Kimura, Hajime; Wu, Chih Chiang; Yoshida, Hiroshi; Chen, Min Cheng; MING-HAN LIAO; Chang, Shou Zen; Yamazaki, Shunpei
國立交通大學 2017-04-21T06:49:53Z Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou
國立交通大學 2014-12-08T15:25:51Z Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces Chang, WJ; Ker, MD
中原大學 1998-11-10 Layout structure for improving resistance uniformity of a polysilicon resistor Shen-Wen Cheng;Chun-Lin Cheng
國立交通大學 2014-12-08T15:21:45Z Layout Styles to Improve CDM ESD Robustness of Integrated Circuits in 65-nm CMOS Process Ker, Ming-Dou; Lin, Chun-Yu; Chang, Tang-Long
國立臺灣大學 1985-09 Layout System Vol. 1:Computer-Aided VLSI Routing Design Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學 1985 Layout System Vol. 2:Symbolic Layout and Circuit Compaction for CMOS IC Design Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學 1985-09 Layout System Vol. 3:Design and Implementation of a Design Rule Checking System for VLSI Design Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立臺灣大學 1986-09 Layout System Vol. 4:an Automatic Placement System for VLSI Layouts Chen, S. J.; 龐台銘; 于惠中; 馮武雄; Chen, S. J.; 龐台銘; 于惠中; Feng, Wu-Shiung
國立交通大學 2014-12-08T15:25:40Z Layout techniques for on-chip interconnect inductance reduction Tu, SW; Jou, JY; Chang, YW
臺大學術典藏 2018-09-10T04:53:44Z Layout techniques for on-chip interconnect inductance reduction Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG
義守大學 2011 Layout 設計與電磁相容之研究 陳安吉; An-Chi chen
國立中山大學 2006-08 Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis X.L. Li;S.J. Wang;K.S.M. Li
國立中山大學 2006-08 Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage K.L. Peng;S.J. Wang;K.S.M. Li
國立交通大學 2019-10-05T00:09:48Z Layout-Based Dual-Cell-Aware Tests Wu, Tse-Wei; Lee, Dong-Zhen; Wu, Kai-Chiang; Huang, Yu-Hao; Chen, Ying-Yen; Chen, Po-Lin; Chern, Mason; Lee, Jih-Nung; Kao, Shu-Yi; Chao, Mango C. -T.
國立交通大學 2017-04-21T06:56:48Z Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults-From Device to Circuit Level Huang, Hsuan-Ming; Wen, Charles H. -P.
臺大學術典藏 2018-09-10T15:33:11Z Layout-Dependent Effects-Aware Analytical Analog Placement Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG
國立交通大學 2014-12-08T15:27:35Z Layout-Dependent Stress Effect on High-Frequency Characteristics and Flicker Noise in Multifinger and Donut MOSFETs Yeh, Kuo-Liang; Guo, Jyh-Chyurn
臺大學術典藏 2018-09-10T15:23:14Z Layout-dependent-effects-aware analytical analog placement Ou, H.-C.;Tseng, K.-H.;Liu, J.-Y.;Wu, I.-P.;Chang, Y.-W.; Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2022-02-21T23:31:24Z LayoutTransformer: Scene Layout Generation with Conceptual and Spatial Diversity Yang, Cheng Fu; Fan, Wan Cyuan; Yang, Fu En; Wang, Yu Chiang Frank
臺大學術典藏 2021-01-04T05:52:14Z Laypeople's source selection in online health information-seeking process Chi, Y.;He, D.;Jeng, W.; Chi, Y.; He, D.; Jeng, W.; Wei Jeng

Showing items 544726-544750 of 2348570  (93943 Page(s) Totally)
<< < 21785 21786 21787 21788 21789 21790 21791 21792 21793 21794 > >>
View [10|25|50] records per page