| 國立政治大學 |
2014-12 |
Logging and analyzing long-term mobile user behavior
|
Wu, Hui Yin; 吳蕙盈; Liao, Wen-Hung; 廖文宏; Chen, Po-Ming; 陳柏銘; Hsu, Chih Yu; 許志毓; Li, Tsai-Yen; 李蔡彥 |
| 國立政治大學 |
2013.05 |
LOGGING AND ANALYZING MOBILE USER BEHAVIORS
|
李蔡彥; Chen,Po-Ming;Wu,Hui-Yin;Hsu,Chih-Yu;Liao,Wen-Hung;Li,Tsai-Yen |
| 臺大學術典藏 |
2018-09-10T07:04:10Z |
Logic 90 nm n-channel field effect transistor current and speed enhancements through external mechanical package straining
|
Liao, W.-S.; Huang, S.-Y.; Tang, M.-C.; Liaw, Y.-G.; Chen, K.-M.; Shih, T.; Tsen, H.-C.; Chung, L.; Liu, C.W.; CHEE-WEE LIU |
| 國立臺灣大學 |
2009 |
Logic and Circuit Simulation
|
Huang, J.-L.; Koh, C.-K.; Cauley, S. F. |
| 臺大學術典藏 |
2020-06-11T06:50:36Z |
Logic and Circuit Simulation
|
Huang, J.-L.;Koh, C.-K.;Cauley, S.F.; Huang, J.-L.; Koh, C.-K.; Cauley, S.F.; JIUN-LANG HUANG |
| 國立臺灣大學 |
2006 |
Logic and Fault Simulation
|
Huang, J.-L.; Li, James C.-M.; Walker, Duncan M. (Hank) |
| 元智大學 |
2014-05-21 |
Logic Block and Design Methodology for Via-configurable Structured ASIC using Dual Supply Voltages
|
Ta-Kai Lin; Kuen-Wey Lin; Chang-Hao Chiu; Lin R.-B. |
| 國立交通大學 |
2017-04-21T06:50:00Z |
Logic Block and Design Methodology for Via-Configurable Structured ASIC Using Dual Supply Voltages
|
Lin, Ta-Kai; Lin, Kuen-Wey; Chiu, Chang-Hao; Lin, Rung-Bin |
| 義守大學 |
2010-09 |
Logic Circuit Design by Neural NeTwork and PSO Algorithm
|
Jen-Pin Yang;Chih-Kung Kung;Fang-Tsung Liu;Yu-Ju Chen;Chuo-Yean Chang;Rey-Chue Hwang |
| 國立政治大學 |
2017 |
Logic control for story graphs in 3D game narratives
|
Wu, Hui-Yin;Li, Tsai-Yen;Christie, Marc; 李蔡彥 |
| 國立臺灣海洋大學 |
2014 |
Logic Control of Enzyme-Like Gold Nanoparticles for Selective Detection of Lead and Mercury Ions
|
Chia-Wen Lien;Yu-Ting Tseng;Chih-Ching Huang;Huan-Tsung Chang |
| 臺大學術典藏 |
2018-09-10T14:59:40Z |
Logic control of enzyme-like gold nanoparticles for selective detection of lead and mercury ions
|
Lien, C.-W.; Tseng, Y.-T.; Huang, C.-C.; Chang, H.-T.; Lien, C.-W.; Tseng, Y.-T.; Huang, C.-C.; Chang, H.-T.; HUAN-TSUNG CHANG |
| 元智大學 |
2018-03-19 |
Logic Optimization with Considering Boolean Relations
|
陳勇志; Tung-Yuan Lee; Chia-Cheng Wu; Chia-Chun Lin; Chun-Yao Wang |
| 元智大學 |
2010-12 |
Logic Performance of 40 nm InAslInxGat_xAs Composite Channel HEMTs
|
Faiz Aizad; Heng-Tung Hsu; Chien-I Kuo; Li-Han Hsu; Chien-Ying Wu; Edward Yi; Guo-Wei Huang; Szu-ping Tsai |
| 元智大學 |
2010-12 |
Logic Performance of 40 nm InAslInxGat_xAs Composite Channel HEMTs
|
Faiz Aizad; Heng-Tung Hsu; Chien-I Kuo; Li-Han Hsu; Chien-Ying Wu; Edward Yi; Guo-Wei Huang; Szu-ping Tsai |
| 元智大學 |
2010-12 |
Logic Performance of 40 nm InAslInxGat_xAs Composite Channel HEMTs
|
Faiz Aizad; Heng-Tung Hsu; Chien-I Kuo; Li-Han Hsu; Chien-Ying Wu; Edward Yi; Guo-Wei Huang; Szu-ping Tsai |
| 臺大學術典藏 |
2018-09-10T03:46:51Z |
Logic Programming with Recurrence Domains
|
JIEH HSIANG; JIEH HSIANG; JIEH HSIANG |
| 國立臺灣大學 |
1992 |
Logic Programming with Recurrence Domains
|
Chen, H.; 項潔; Chen, H.; Hsiang, Jieh |
| 臺大學術典藏 |
2020-05-04T07:58:54Z |
Logic Programming with Recurrence Domains.
|
JIEH HSIANG; Hsiang, Jieh; Chen, Hong |
| 淡江大學 |
1993-12-02 |
Logic programs with conflict resolution
|
洪文斌; Horng, Wen-bing; 楊超植; Yang, Chao-chih |
| 淡江大學 |
1993-12 |
Logic programs with conflict resolution = 邏輯程式中之矛盾解決
|
Horng, Wen-bing; 洪文斌; Yang, Chao-chih; 楊超植 |
| 國立交通大學 |
2014-12-08T15:03:45Z |
LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS
|
HWANG, TT; OWENS, RM; IRWIN, MJ; WANG, KH |
| 國立臺灣大學 |
2009 |
Logic Synthesis in a Nutshell
|
Jiang, Jie-Hong R.; Devadas, Srinivas |
| 臺大學術典藏 |
2018-09-10T07:43:11Z |
Logic Synthesis in a Nutshell
|
Jie-Hong R. Jiang;Srinivas Devadas; Jie-Hong R. Jiang; Srinivas Devadas; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:12Z |
Logic Synthesis in a Nutshell
|
Jiang, J.H.;Devadas, S.; Jiang, J.H.; Devadas, S.; JIE-HONG JIANG |
