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顯示項目 558781-558790 / 2348439 (共234844頁)
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| 國立成功大學 |
2012-06 |
Low-power context-based adaptive binary arithmetic encoder using an embedded cache
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Lei, S. -F.; Lo, C. -C.; Kuo, C. -C.; Shieh, M. -D. |
| 國立交通大學 |
2014-12-08T15:25:28Z |
Low-power data address bus encoding method
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Weng, TH; Chiao, WH; Shann, JJJ; Chung, CP; Lu, J |
| 臺大學術典藏 |
2018-09-10T06:38:17Z |
Low-power delay buffer circuit
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T. D. Chiueh; P. C. Hsieh; TZI-DAR CHIUEH |
| 國立中山大學 |
1997 |
Low-Power Design for Real-Time Systems
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Sheng-Tzong Cheng;Chia-Mei Chen;Jing-Wen Hwang |
| 臺大學術典藏 |
2018-09-10T05:59:23Z |
Low-power design methodology for DSP systems using multirate approach
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Wu, An-Yeu; Ray Liu, K.J.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; AN-YEU(ANDY) WU; Wu, An-Yeu;Ray Liu, K.J.;Zhang, Zhongying;Nakajima, Kazuo;Raghupathy, Arun |
| 國立交通大學 |
2015-07-21T11:21:11Z |
Low-Power Displays With Dye-Doped Bistable Chiral-Tilted Homeotropic Nematic Liquid Crystals
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Lee, Yun-Han; Huang, Kuan-Chung; Lee, Wei; Chen, Chao-Yuan |
| 國立臺灣科技大學 |
2009-02 |
Low-power divide-by-3 injection-locked frequency dividers implemented with injection transformers
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Jang, S.L.;Chang, C.W.;Cheng, W.C.;Lee, C.F.;Juang, M.H. |
| 國立交通大學 |
2014-12-08T15:05:56Z |
LOW-POWER DYNAMIC TERNARY LOGIC
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WANG, JS; WU, CY; TSAI, MK |
| 國立成功大學 |
2015-03 |
Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator
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Peng, Chih-Hsiang; Lin, Po-Chuan; Barma, Shovan; Wang, Jhing-Fa; Peng, Hong-Yuan; Bharanitharan, Karunanithi; Kuan, Ta-Wen |
| 淡江大學 |
2013-01 |
Low-Power Fast-Settling Low-Dropout Regulator Using a Digitally Assisted Voltage Accelerator for DVFS Application
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Yang, Wei-Bin; Wang, Chi Hsiung; Chang, Hsiang Hsiung; Hong, Ming Hao; Shen, Jsung Mo |
顯示項目 558781-558790 / 2348439 (共234844頁)
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