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Showing items 575291-575315 of 2348570 (93943 Page(s) Totally)
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| 國立交通大學 |
2014-12-16T06:15:42Z |
MEMORY-BASED FFT/IFFT PROCESSOR AND DESIGN METHOD FOR GENERAL SIZED MEMORY-BASED FFT PROCESSOR
|
LEE, Chen-Yi; Hsiao, Chen-Fong; Chen, Yuan |
| 國立高雄應用科技大學 |
1998-12 |
Memory-Based Function Approzimation
|
Shieh, Chin-Shiuh;Pan, Jenq-Shyang |
| 臺大學術典藏 |
2018-09-10T07:10:54Z |
Memory-Based Judgments: The Role of Information Typicality and Processing Ability
|
Lien, Nai-Hwa;Douglas M. Stayman; Lien, Nai-Hwa; Douglas M. Stayman; NAI-HWA LIEN |
| 實踐大學 |
2002 |
Memory-based sigma-pi-sigma neural network
|
Li, C.K. |
| 臺大學術典藏 |
2018-09-10T14:54:02Z |
Memory-based two-dimensional-parallel differential matched filter correlator for global navigation satellite system code acquisition
|
Chen, C.-W.;Chen, S.-H.;Tsao, H.-W.;Mao, W.-L.; Chen, C.-W.; Chen, S.-H.; Tsao, H.-W.; Mao, W.-L.; HEN-WAI TSAO |
| 中華大學 |
2006 |
Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
Memory-Efficiency Multiplierless VLSI Architecture for 2-D DWT Using 9/7 Wavelet Filter
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Memory-Efficiency Multiplierless VLSI Architecture for 2-D DWT Using 9/7 Wavelet Filter
|
謝曜式; Shieh, Yaw-Shih |
| 中華大學 |
2006 |
Memory-Efficient and Fast Architectures for Forward and Inverse DCT with Multiplierless Operation
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Memory-Efficient and Fast Architectures for Forward and Inverse DCT with Multiplierless Operation,
|
謝曜式; Shieh, Yaw-Shih |
| 國立聯合大學 |
2007 |
Memory-Efficient and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation
|
Tze-Yun Sung, Hsi-Chin Hsin |
| 中華大學 |
2007 |
Memory-Efficient and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2007 |
Memory-EfficiEnt and High-Performance 2-D DCT and IDCT Processors Based on CORDIC Rotation
|
宋志雲; Sung, Tze-Yun |
| 國立聯合大學 |
2007 |
Memory-Efficient and High-Performance Parallel-Pipelined Architectures for 5/3 Forward and Inverse Discrete Wavelet Transform
|
Tze-Yun Sung, Hsi-Chin Hsin |
| 中華大學 |
2007 |
Memory-Efficient and High-Performance Parallel-Pipelined Architectures for 5/3 Forward and Inverse Discrete Wavelet Transform
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2007 |
Memory-EfficiEnt and High-Performance Parallel-Pipelined Architectures for 5/3 Forward and Inverse Discrete Wavelet Transform
|
宋志雲; Sung, Tze-Yun |
| 國立聯合大學 |
2007 |
Memory-Efficient and High-Speed Line-Based Architecture for 2-D Discrete Wavelet Transform with Lifting Scheme
|
Tze-Yun Sung, Hsi-Chin Hsin |
| 中華大學 |
2007 |
Memory-Efficient and High-Speed Line-Based Architecture for 2-D Discrete Wavelet Transform with Lifting Scheme
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
Memory-Efficient and High-Speed Split-Radix FFT/IFFT Processor Based on Pipelined CORDIC Rotations
|
宋志雲; Sung, Tze-Yun |
| 國立交通大學 |
2014-12-08T15:17:00Z |
Memory-efficient architecture for JPEG 2000 coprocessor with large tile image
|
Wu, BF; Lin, CF |
| 淡江大學 |
2009 |
Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000
|
李偉銘; Li, Wei-ming |
| 淡江大學 |
2009 |
Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000
|
Li, Wei-ming; Hsia, Chih-Hsien; Chiang, Jen-Shiun |
| 淡江大學 |
2011-07 |
Memory-efficient architecture of 2-D lifting-based discrete wavelet transform
|
Hsia, Chih-Hsien; Li, Wei-Ming; Chiang, Jen-Shiun |
| 國立成功大學 |
2015-05 |
Memory-efficient buffering method and enhanced reference template for embedded automatic speech recognition system
|
Chou, Chih-Hung; Kuan, Ta-Wen; Lin, Po-Chuan; Chen, Bo-Wei; Wang, Jhing-Fa |
Showing items 575291-575315 of 2348570 (93943 Page(s) Totally)
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