| 東海大學 |
2011 |
Performance-based parallel loop self-scheduling using hybrid OpenMP and MPI programming on multicore SMP clusters
|
Yang C.-T., Wu C.-C., Chang J.-H. |
| 東海大學 |
2011-06 |
Performance-based Parallel Loop Self-Scheduling Using Hybrid OpenMP and MPI Programming on Multicore SMP Clusters.
|
Yang, Chao-Tung, Wu, Chao-Chin and Chang, Jen-Hsiang.; 楊朝棟 |
| 亞洲大學 |
2005 |
Performance-Based Parallel Scheduling on Grid Environments
|
Wen-Chung Shih; Chao-Tung Yang; S. S. Tseng |
| 臺大學術典藏 |
2012 |
Performance-Based Plastic Design and Energy-Based Evaluation of Seismic Resistant RC Moment Frame
|
Liao, Wen-Cheng; Goel, Subhash C.; Liao, Wen-Cheng; Goel, Subhash C. |
| 國立臺灣大學 |
2012 |
Performance-Based Plastic Design and Energy-Based Evaluation of Seismic Resistant RC Moment Frame
|
Liao, Wen-Cheng; Goel, Subhash C. |
| 國立交通大學 |
2014-12-08T15:07:08Z |
Performance-based workload distribution on grid environments
|
Shih, Wen-Chung; Yang, Chao-Tung; Chen, Tsui-Ting; Tseng, Shian-Shyong |
| 亞洲大學 |
2007-05 |
Performance-based Workload Distribution on Grid Environments
|
曾憲雄;Tseng, Shian-Shyong |
| 東海大學 |
2007 |
Performance-based workload distribution on grid environments
|
Shih W.-C., Yang C.-T., Chen T.-T., Tseng S.-S. |
| 國立交通大學 |
2017-04-21T06:56:47Z |
Performance-Complexity Analysis for MAC ML-Based Decoding With User Selection
|
Lu, Hsiao-feng; Elia, Petros; Singh, Arun Kumar |
| 國立交通大學 |
2014-12-08T15:08:09Z |
Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning
|
Wu, Meng-Chen; Lu, Ming-Ching; Chen, Hung-Ming; Jou, Jing-Yang |
| 南台科技大學 |
1995-01 |
Performance-Directed Compaction for VLSI Symbolic Layout
|
Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; Ting-Chun Chang;王立洋 |
| 國立成功大學 |
2012-11 |
Performance-driven Analog Placement Considering Monotonic Current Paths
|
Wu, Po-Hsun; Lin, Mark Po-Hung; Chen, Yang-Ru; Chou, Bing-Shiun; Chen, Tung-Chieh; Ho, Tsung-Yi; Liu, Bin-Da |
| 國立交通大學 |
2014-12-08T15:21:46Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay
|
Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:22:04Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
|
Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 元智大學 |
2009-04 |
Performance-driven dual-rail insertion for chip-level pre-fabricated design
|
陳福偉; 劉一宇 |
| 元智大學 |
2010-12 |
Performance-driven dual-rail routing architecture for structured ASIC design style
|
Fu-Wei Chen; Yi-Yu Liu |
| 南台科技大學 |
1993 |
Performance-Driven Global Routing Based on Simulated Evolution
|
Lih-Yang Wang; Bin-Da Liu; Yen-Tai Lai; Ming-Yuan Yeh; 王立洋;劉濱達 |
| 中原大學 |
2006-08 |
Performance-Driven Global Routing in the Present of Obstacles
|
Wu, Wei-Yu;Hsieh, Tsai-Ming;Huang, Hsin-Hsiung |
| 臺大學術典藏 |
2018-09-10T04:12:52Z |
Performance-driven placement for dynamically reconfigurable FPGAs
|
Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG |
| 南華大學 |
2002-10 |
Performance-driven placement for dynamically reconfigurable FPGAs
|
吳光閔;Wu, Guang-Ming;Lin, Jai-Ming;Chang, Yao-Wen |
| 國立臺灣大學 |
2002 |
Performance-driven placement for dynamically reconfigurable FPGAs
|
Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen |
| 臺大學術典藏 |
2021-12-14T23:12:45Z |
Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems
|
Chen, Ming Hung; YAO-WEN CHANG; Wang, Jun Jie |
| 國立交通大學 |
2017-04-21T06:55:34Z |
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
|
Huang, Chien-Chih; Wey, Chin-Long; Chen, Jwu-E; Luo, Pei-Wen |
| 中華大學 |
2008 |
Performance-Effective and Contention-Free Broadcasts on Irregular Network with Heterogeneous Workstations
|
游坤明; Yu, K.M. |
| 中華大學 |
2008 |
Performance-Effective and Contention-Free Broadcasts on Irregular Network with Heterogeneous Workstations
|
許慶賢; Hsu, Ching-Hsien |
