臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
國立交通大學	2014-12-08T15:07:08Z	Performance-based workload distribution on grid environments	Shih, Wen-Chung; Yang, Chao-Tung; Chen, Tsui-Ting; Tseng, Shian-Shyong
亞洲大學	2007-05	Performance-based Workload Distribution on Grid Environments	曾憲雄;Tseng, Shian-Shyong
東海大學	2007	Performance-based workload distribution on grid environments	Shih W.-C., Yang C.-T., Chen T.-T., Tseng S.-S.
國立交通大學	2017-04-21T06:56:47Z	Performance-Complexity Analysis for MAC ML-Based Decoding With User Selection	Lu, Hsiao-feng; Elia, Petros; Singh, Arun Kumar
國立交通大學	2014-12-08T15:08:09Z	Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning	Wu, Meng-Chen; Lu, Ming-Ching; Chen, Hung-Ming; Jou, Jing-Yang
南台科技大學	1995-01	Performance-Directed Compaction for VLSI Symbolic Layout	Lih-Yang Wang; Yen-Tai Lai; Bin-Da Liu; Ting-Chun Chang;王立洋
國立成功大學	2012-11	Performance-driven Analog Placement Considering Monotonic Current Paths	Wu, Po-Hsun; Lin, Mark Po-Hung; Chen, Yang-Ru; Chou, Bing-Shiun; Chen, Tung-Chieh; Ho, Tsung-Yi; Liu, Bin-Da
國立交通大學	2014-12-08T15:21:46Z	Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay	Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang
國立交通大學	2014-12-08T15:22:04Z	Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay	Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang
元智大學	2009-04	Performance-driven dual-rail insertion for chip-level pre-fabricated design	陳福偉; 劉一宇

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