| 國立交通大學 |
2014-12-08T15:30:05Z |
A 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opamps
|
Fang, Bing-Nan; Wu, Jieh-Tsorng |
| 臺大學術典藏 |
2018-09-10T09:25:30Z |
A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter
|
C-C Ho;T-C Lee; C-C Ho; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2019-10-31T07:12:32Z |
A 10-bit 200MS/s Capacitor-Sharing Pipeline ADC
|
HSIN-SHU CHEN;Hsin-Shu Chen;Ching-Hua Yang;Yi-Chun Hsieh;Chien-Jian Tseng; Chien-Jian Tseng; Yi-Chun Hsieh; Ching-Hua Yang; Hsin-Shu Chen; HSIN-SHU CHEN |
| 中華大學 |
2006 |
A 10-bit 250-MSPS Digital to Analog Converter for WLAN Applications
|
田慶誠; Tien, Ching-Cheng |
| 中華大學 |
2006 |
A 10-bit 250-MSPS Digital to Analog Converter for WLAN Applications
|
王志湖; Wang, Chih-Hu |
| 臺大學術典藏 |
2021-05-24T13:07:20Z |
A 10-bit 300 MS/s pipeline ADC with time-domain MDAC
|
HSIN-SHU CHEN; Tseng, Chien Jian; Chuang, Yu Wei; Chang, Chun Wei |
| 臺大學術典藏 |
2021-09-02T00:04:59Z |
A 10-bit 300 MS/s pipeline ADC with time-domain MDAC
|
Chen H.-S;Tseng C.-J;Chuang Y.-W;Chang C.-W.; Chen H.-S; Tseng C.-J; Chuang Y.-W; Chang C.-W.; HSIN-SHU CHEN |
| 國立交通大學 |
2014-12-08T15:29:24Z |
A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation
|
Fang, Bing-Nan; Wu, Jieh-Tsorng |
| 國立臺灣科技大學 |
2015 |
A 10-bit 40 MS/s successive approximation register analog-to-digital converter with Vcm-based method for wireless communications
|
Lai, W.C. |
| 國立臺灣科技大學 |
2016 |
A 10-bit 40 MS/s successive approximation register analog-to-digital converter with Vcm-based method for wireless communications
|
Lai, W.C. |
| 臺大學術典藏 |
2020-06-11T06:34:55Z |
A 10-bit 40-MS/s Time-Domain Two-Step ADC with Short Calibration Time
|
Chen, L.-J.;Liu, S.-I.; Chen, L.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:21:00Z |
A 10-bit 400-MS/s 36-mW interleaved ADC
|
Huang, Y.-C.;Lin, C.-Y.;Lee, T.-C.; Huang, Y.-C.; Lin, C.-Y.; Lee, T.-C.; TAI-CHENG LEE |
| 臺大學術典藏 |
2018-09-10T07:45:58Z |
A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications
|
Nai-Kuan Chou; Pang, W.-Y.; Wang, C.-S.; Chang, Y.-K.; Chou, N.-K.; Wang, C.-K.; Nai-Kuan Chou |
| 臺大學術典藏 |
2020-03-09T07:30:51Z |
A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications
|
Pang W.-Y.; Wang C.-S.; Chang Y.-K.; NAI-KUAN CHOU; Wang C.-K. |
| 義守大學 |
1998-08 |
A 10-Bit 50MHz Analog-to-Digital Converter Using Pipeline Architecture and Current-Mode Techniques
|
林啟元;Lin, Kai-yuen;涂振嘉;Twu, Chen-chia |
| 淡江大學 |
2005 |
A 10-bit 50Msample/s pipelined analog-to-digital converter
|
黃世麟; Huang, Shih-lin |
| 國立虎尾科技大學 |
2007 |
A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter
|
Lu, Chi-Chang;Lee, Tsung-Sum |
| 亞洲大學 |
2015-01 |
A 10-bit current-steering CMOS digital to analog converter
|
易昶霈;Yi, Chang-Pei |
| 亞洲大學 |
2015-01 |
A 10-bit current-steering CMOS digital to analog converter
|
易昶霈;Yi, Chang-Pei |
| 亞洲大學 |
2015-01 |
A 10-bit current-steering CMOS digital to analog converter
|
Yi, 易昶霈 Chang-Pei |
| 亞洲大學 |
2015/01 |
A 10-bit current-steering CMOS digital to analog converter
|
Yi, 易昶霈 Chang-Pei |
| 亞洲大學 |
2015-01 |
A 10-bit current-steering CMOS digital to analog converter
|
Yi, 易昶霈；Chang-Pei |
| 亞洲大學 |
2015-01 |
A 10-bit current-steering CMOS digital to analog converter
|
Yi), 易昶霈(Chang-Pei |
| 臺大學術典藏 |
2020-06-11T06:45:53Z |
A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS
|
Cheng, W.-S.;Hsieh, M.-H.;Hung, S.-H.;Hung, S.-Y.;Chen, C.C.-P.; Cheng, W.-S.; Hsieh, M.-H.; Hung, S.-H.; Hung, S.-Y.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 國立暨南國際大學 |
2013 |
A 10-Bit DAC With 1.6-Bit Interpolation Cells for Compact LCD Column Driver ICs
|
蕭敬民?; Hsiao, CM |
| 國立暨南國際大學 |
2013 |
A 10-Bit DAC With 1.6-Bit Interpolation Cells for Compact LCD Column Driver ICs
|
林佑昇; Lin, YS |
| 國立暨南國際大學 |
2013 |
A 10-bit DAC with offset-adjustable op-amp for LCD column driver applications
|
蕭敬民?; Hsiao, CM |
| 國立暨南國際大學 |
2013 |
A 10-bit DAC with offset-adjustable op-amp for LCD column driver applications
|
林佑昇; Lin, YS |
| 國立暨南國際大學 |
2013 |
A 10-bit DAC with offset-adjustable op-amp for LCD column driver applications
|
Yin, PY; Yin, PY |
| 國立暨南國際大學 |
2008 |
A 10-bit LCD column driver with piecewise linear digital-to-analog converters?
|
盧志文; Lu, CW |
| 臺大學術典藏 |
2020-06-11T06:21:01Z |
A 10-bit piplined A/D converter with split calibration and opamp-sharing technique
|
TAI-CHENG LEE; Lee, T.-C.; Huang, Y.-C.; Hung, L.-H.; Hung, L.-H.;Huang, Y.-C.;Lee, T.-C. |
| 國立暨南國際大學 |
2012 |
A 10-bit Resistor-Floating-Resistor-String DAC (RFR-DAC) for High Color-Depth LCD Driver ICs
|
林佑昇; Lin, YS |
| 國立成功大學 |
2003-04-30 |
A 10-fold improvement in the precision of boron isotopic analysis by negative thermal ionization mass spectrometry
|
Shen, Jason Jiun-San; You, Chen-Feng |
| 臺大學術典藏 |
2018-09-10T09:50:32Z |
A 10-Gb/s adaptive parallel receiver with joint XTC and DFE using power detection
|
Shih-Yuan Kao;Shen-Iuan Liu; Shih-Yuan Kao; Shen-Iuan Liu; SHEN-IUAN LIU |
| 臺大學術典藏 |
2021-04-22T08:10:02Z |
A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS
|
Lin, Y.-C.; Tsao, H.-W.; HEN-WAI TSAO |
| 國立臺灣大學 |
2009 |
A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology
|
Lu, Jian-Hao; Chen, Ke-Hou; Liu, Shen-Iuan |
| 臺大學術典藏 |
2020-06-11T06:34:53Z |
A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology (vol 56, pg 97, 2009)
|
Lu, Jian-Hao;Chen, Ke-Hou;Liu, Shen-Iuan; Lu, Jian-Hao; Chen, Ke-Hou; Liu, Shen-Iuan; SHEN-IUAN LIU |
| 國立臺灣大學 |
2007 |
A 10-Gb/s inductorless CMOS limiting amplifier with third-order interleaving active feedback
|
Huang, Huei-Yan; Chien, Jun-Chau; Lu, Liang-Hung |
| 臺大學術典藏 |
2021-03-12T08:41:03Z |
A 10-Gb/s Inductorless CMOS Limiting Amplifier with Third-Order Interleaving Active Feedback
|
JUN-CHAU CHIEN; 簡俊超; JUN-CHAU CHIEN |
| 國立交通大學 |
2014-12-08T15:25:38Z |
A 10-Gb/s laser diode driver in 0.35 mu m BiCMOS technology
|
Wang, TY; Chen, WZ; Tsai, CM; Huang, LR; Li, DU |
| 國立交通大學 |
2014-12-08T15:47:46Z |
A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-mu m CMOS Technology
|
Huang, Shih-Hao; Chen, Wei-Zen; Chang, Yu-Wei; Huang, Yang-Tung |
| 國立交通大學 |
2015-07-21T08:28:41Z |
A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression
|
Su, Ming-Chiuan; Chen, Wei-Zen; Wu, Pei-Si; Chen, Yu-Hsiang; Lee, Chao-Cheng; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-08T15:20:15Z |
A 10-Gbps CMOS Single Chip Optical Receiver with 2-D Meshed Spatially-Modulated Light Detector
|
Huang, Shih-Hao; Chen, Wei-Zen |
| 臺大學術典藏 |
2018-09-10T05:29:26Z |
A 10-GHz CMOS PLL with an Agile VCO Calibration
|
Y.-J. Lai; T.-H Lin; TSUNG-HSIEN LIN |
| 國立臺灣科技大學 |
2014 |
A 10-GHz low power CMOS voltage controlled oscillator chip design for wireless application
|
Lai W.-C., Huang J.-F., Hsu C.-M., Lay W.-T. |
| 國立成功大學 |
2021-10 |
A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR > 64/50 dBc Over the First/Second Nyquist Zone
|
Huang;Hung-Yi;Chen;Xin-Yu;Kuo;Tai-Haur |
| 國立成功大學 |
2021 |
A 10-GS/s NRZ/Mixing DAC with Switching-Glitch Compensation Achieving SFDR >64/50 dBc over the First/Second Nyquist Zone
|
Huang, Huang H.-Y.;Chen, X.-Y.;Kuo, T.-H. |
| 臺大學術典藏 |
2021-09-06T03:52:41Z |
A 10-item Fugl-Meyer Motor Scale Based on Machine Learning
|
Lin G.-H.; CHIEN-YU HUANG; Lee S.-C.; Chen K.-L.; Lien J.-J.J.; Chen M.-H.; Huang Y.-H.; Hsieh C.-L. |
| 臺大學術典藏 |
2022-02-10T08:29:45Z |
A 10-item Fugl-Meyer Motor Scale Based on Machine Learning
|
Lin G.-H.; Huang C.-Y.; Lee S.-C.; Chen K.-L.; Lien J.-J.J.; Chen M.-H.; Huang Y.-H.; CHING-LIN HSIEH |
| 國立成功大學 |
2021 |
A 10-item Fugl-Meyer Motor Scale Based on Machine Learning
|
Lin, G.-H.;Huang, C.-Y.;Lee, S.-C.;Chen, K.-L.;Lien, J.-J.J.;Chen, M.-H.;Huang, Y.-H.;Hsieh, C.-L. |
