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教育部委托研究计画 计画执行:国立台湾大学图书馆
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显示项目 912511-912520 / 2343346 (共234335页)
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每页显示[10|25|50]项目
| 國立中山大學 |
2003-06-25 |
VLIW DSP架構之增進指令並行度之向量化運算機制
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楊得鑫 |
| 中華大學 |
2004 |
VLIW Processor with Embedded Watchdog Processor for Control Flow Error Detection
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陳永源; Chen, Yung-Yuan |
| 淡江大學 |
2024-07-31T04:08:27Z |
Vloggers and consumer choices in the hotel and hospitality sector: The double-edged sword of discounts
|
Ni, Yensen |
| 國立成功大學 |
2005-04 |
VLSI architectural design tradeoffs for sliding-window Log-MAP decoders
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Wu, Chien-Ming; Shieh, Ming-Der; Wu, Chien-Hsing; Hwang, Yin-Tsung; Chen, Jun-Hong |
| 國立成功大學 |
2002-08 |
VLSI architecture and implementation for speech recognizer based on discriminative Bayesian neural network
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Wang, Jhing-Fa; Wang, Jia-Ching; Suen, An-Nan; Wu, Chung-Hsien; Li, Fan-Min |
| 臺大學術典藏 |
2018-09-10T04:07:51Z |
VLSI architecture design and implementation for TWOFISH block cipher
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Lai, Y.-K.; Chen, L.-G.; Lai, J.-Y.; Parng, T.-M.; LIANG-GEE CHEN |
| 國立臺灣大學 |
2001-07-31 |
VLSI Architecture Design and Implementation of IF and Baseband Analog Front End for Digital Multimedia Wireless Receiver (II)
|
汪重光 |
| 亞洲大學 |
2002-05-16 |
VLSI ARCHITECTURE DESIGN FOR TWOFISH BLOCK CIPHER
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Li-Chung Chang ;Yeong-Kang Lai; Liang-Gee Chen;Jian-Yi La;Tai-Ming Parng |
| 中國文化大學 |
1997-06 |
VLSI Architecture Design of a High Performance Clustering Analyzer
|
賴茂富 |
| 元智大學 |
Dec-15 |
VLSI Architecture Design of FM0/Manchester Codec with 100% Hardware Utilization Rate for DSRC-Based Sensor Nodes in ITS Applications
|
Yu-Hsuan Lee; Cheng-Wei Pan; Fang-Hsu Tsai |
显示项目 912511-912520 / 2343346 (共234335页)
<< < 91247 91248 91249 91250 91251 91252 91253 91254 91255 91256 > >>
每页显示[10|25|50]项目
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