| 國立交通大學 |
2014-12-08T15:01:53Z |
VLSI cell placement on arbitrarily-shaped rectilinear regions using neural networks with calibration nodes - Comments
|
Huang, KY |
| 國立中山大學 |
2001-09 |
VLSI circuit design of 16-Mbps IrDA VFIR transceivers
|
C.C. Wang;C.W. Chen;Y.L. Huang |
| 國立交通大學 |
2014-12-08T15:01:29Z |
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
|
Chang, RI; Hsiao, PY |
| 國立交通大學 |
2019-04-02T05:59:32Z |
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
|
Chang, RI; Hsiao, PY |
| 臺大學術典藏 |
2018-09-10T06:32:26Z |
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
|
RAY-I CHANG;HSIAO, PY;CHANG, RI; CHANG, RI; HSIAO, PY; RAY-I CHANG |
| 臺大學術典藏 |
2018-09-10T08:34:15Z |
VLSI design and implementation of density-based spike classification for neuroprosthetic applications
|
Cheng, L.-F.;Chen, T.-C.;Chen, L.-G.; Cheng, L.-F.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立聯合大學 |
2004 |
VLSI Design and Implementation of The Re-configurable 2-D Von Neumann Cellular Automata Bases Generator for The Image Processing Applications
|
陳榮堅, 賴瑞麟 |
| 國立交通大學 |
2014-12-08T15:46:11Z |
VLSI design for high-speed LZ-based data compression
|
Chen, JM; Wei, CH |
| 國立中山大學 |
1998-06 |
VLSI design of A 1.0 GHz 0.6-µm 8-Bit CLA using PLA-styled all-N-transistor Logic
|
C.C. Wang;K.C. Tsai |
| 國立交通大學 |
2014-12-08T15:27:27Z |
VLSI design of a priority arbitrator for shared buffer ATM switches
|
Lin, YS; Yang, SC; Fang, SJ; Shung, CB |
| 臺大學術典藏 |
2018-09-10T04:13:19Z |
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
|
Hsu, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 國立臺灣大學 |
2002-08 |
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
|
Hsu, Huai-Yi; Wu, An-Yeu |
| 臺大學術典藏 |
2003 |
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems
|
Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu; Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu |
| 國立臺灣大學 |
2003 |
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems
|
Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu |
| 臺大學術典藏 |
2019-10-24T07:57:17Z |
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems
|
吳安宇;AN-YEU(ANDY) WU;An-Yeu Wu;Chih-Hsiu Lin;Ching-Hua Wen;Jen-Chih Kuo; Jen-Chih Kuo; Ching-Hua Wen; Chih-Hsiu Lin; An-Yeu Wu; AN-YEU(ANDY) WU; 吳安宇 |
| 國立臺灣師範大學 |
2019-09-03T10:49:33Z |
VLSI Design of Advanced Encryption Standard
|
葉幸彰; Hsing-Chang Yeh |
| 國立中山大學 |
2000-08 |
VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking
|
Shen-Fu Hsiao;Yor-Chin Tai;Kai-Hsiang Chang |
| 國立中山大學 |
2000-06 |
VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking
|
Shen-Fu Hsiao; Yor-Chin Tai; Kai-Hsiang Chang |
| 國立成功大學 |
2019-01 |
VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications
|
Shiau;Yeu-Horng;Kuo;Yao-Tsung;Chen;Pei-Yin;Hsu;Feng-Yuan |
| 東方設計學院 |
2011-02 |
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm
|
Kuan,; Ta-Wen; Wang, Jhing-Fa; Wang, Jia-Ching; Lin, Po-Chuan; Gu, Gaung-Hui; 林博川; (東方設計學院電子與資訊系) |
| 國立成功大學 |
2012-04 |
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm
|
Kuan, Ta-Wen; Wang, Jhing-Fa; Wang, Jia-Ching; Lin, Po-Chuan; Gu, Gaung-Hui |
| 國立臺灣大學 |
1995-05 |
VLSI design of clustering analyser using systolic arrays
|
Lai, M.F.; Nakano, M.; Wu, Y.P.; Hsieh, C.H. |
| 臺大學術典藏 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 元智大學 |
Feb-15 |
VLSI Design of FM0/Manchester Encoder with Reuse-Oriented Boolean Simplification Technique for DSRC Applications
|
Yu-Hsuan Lee; Cheng-Wei Pan |
