| 淡江大學 |
2005 |
VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications
|
Chiang, Jen-Shiun; Hsia, Chih-Hsien; Chen, Hsin-Jung; Lo, Te-Jung |
| 義守大學 |
2003-10 |
VLSI architecture of modified Euclidean algorithm for Reed-Solomon code
|
Y.W. Chang;T.K. Truong;J.H. Jeng |
| 國立成功大學 |
2020 |
VLSI architecture of polynomial multiplication for BGV fully homomorphic encryption
|
Hsu, Hsu H.-J.;Shieh, M.-D. |
| 國立成功大學 |
2022 |
VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic
|
Teng;You-Tun;Chin;Wen-Long;Chang;Deng-Kai;Chen;Pei-Yin;Chen;Pin-Wei |
| 中華大學 |
2006 |
VLSI Architectures for 2-D Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters
|
宋志雲; Sung, Tze-Yun |
| 中華大學 |
2006 |
VLSI Architectures for 2-D Forward and Inverse Discrete Wavelet Transform Using 4-tap Daubechies Filters
|
謝曜式; Shieh, Yaw-Shih |
| 中原大學 |
2001-10-11 |
VLSI CAD中一些最佳化問題之研究
|
林佑政; Yu-Chung Lin |
| 中原大學 |
1989 |
VLSI CAD數位語音系統之設計
|
王如生; WANG, RU-SHENG |
| 國立交通大學 |
2014-12-08T15:03:00Z |
VLSI cell placement on arbitrarily-shaped rectilinear regions using neural networks with calibration nodes
|
Chang, RI; Hsiao, PY |
| 臺大學術典藏 |
2018-09-10T05:24:37Z |
VLSI cell placement on arbitrarily-shaped rectilinear regions using neural networks with calibration nodes
|
RAY-I CHANG;HSIAO, PY;CHANG, RI; CHANG, RI; HSIAO, PY; RAY-I CHANG |
| 國立交通大學 |
2014-12-08T15:01:53Z |
VLSI cell placement on arbitrarily-shaped rectilinear regions using neural networks with calibration nodes - Comments
|
Huang, KY |
| 國立中山大學 |
2001-09 |
VLSI circuit design of 16-Mbps IrDA VFIR transceivers
|
C.C. Wang;C.W. Chen;Y.L. Huang |
| 國立交通大學 |
2014-12-08T15:01:29Z |
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
|
Chang, RI; Hsiao, PY |
| 國立交通大學 |
2019-04-02T05:59:32Z |
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
|
Chang, RI; Hsiao, PY |
| 臺大學術典藏 |
2018-09-10T06:32:26Z |
VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps
|
RAY-I CHANG;HSIAO, PY;CHANG, RI; CHANG, RI; HSIAO, PY; RAY-I CHANG |
| 臺大學術典藏 |
2018-09-10T08:34:15Z |
VLSI design and implementation of density-based spike classification for neuroprosthetic applications
|
Cheng, L.-F.;Chen, T.-C.;Chen, L.-G.; Cheng, L.-F.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 國立聯合大學 |
2004 |
VLSI Design and Implementation of The Re-configurable 2-D Von Neumann Cellular Automata Bases Generator for The Image Processing Applications
|
陳榮堅, 賴瑞麟 |
| 國立交通大學 |
2014-12-08T15:46:11Z |
VLSI design for high-speed LZ-based data compression
|
Chen, JM; Wei, CH |
| 國立中山大學 |
1998-06 |
VLSI design of A 1.0 GHz 0.6-µm 8-Bit CLA using PLA-styled all-N-transistor Logic
|
C.C. Wang;K.C. Tsai |
| 國立交通大學 |
2014-12-08T15:27:27Z |
VLSI design of a priority arbitrator for shared buffer ATM switches
|
Lin, YS; Yang, SC; Fang, SJ; Shung, CB |
| 臺大學術典藏 |
2018-09-10T04:13:19Z |
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
|
Hsu, H.-Y.; Wu, A.-Y.; AN-YEU(ANDY) WU |
| 國立臺灣大學 |
2002-08 |
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
|
Hsu, Huai-Yi; Wu, An-Yeu |
| 臺大學術典藏 |
2003 |
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems
|
Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu; Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu |
| 國立臺灣大學 |
2003 |
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems
|
Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu |
| 臺大學術典藏 |
2019-10-24T07:57:17Z |
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems
|
吳安宇;AN-YEU(ANDY) WU;An-Yeu Wu;Chih-Hsiu Lin;Ching-Hua Wen;Jen-Chih Kuo; Jen-Chih Kuo; Ching-Hua Wen; Chih-Hsiu Lin; An-Yeu Wu; AN-YEU(ANDY) WU; 吳安宇 |
