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顯示項目 915416-915425 / 2346275 (共234628頁)
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| 東方設計學院 |
2011-02 |
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm
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Kuan,; Ta-Wen; Wang, Jhing-Fa; Wang, Jia-Ching; Lin, Po-Chuan; Gu, Gaung-Hui; 林博川; (東方設計學院電子與資訊系) |
| 國立臺灣大學 |
1995-05 |
VLSI design of clustering analyser using systolic arrays
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Lai, M.F.; Nakano, M.; Wu, Y.P.; Hsieh, C.H. |
| 臺大學術典藏 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
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Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
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Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 元智大學 |
Feb-15 |
VLSI Design of FM0/Manchester Encoder with Reuse-Oriented Boolean Simplification Technique for DSRC Applications
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Yu-Hsuan Lee; Cheng-Wei Pan |
| 義守大學 |
2001-11 |
VLSI Design of Inverse-Free Berlekamp-Massey Algorithm for Reed-Solomon Code
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Truong, T.K. ; Chang, Y.W. ; Jeng, J.H. |
| 元智大學 |
Jan-16 |
VLSI Design of Lossless Frame Recompression Using Multi-Orientation Prediction
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Yu-Hsuan Lee; Yi-Lun You; Yi-Guo Chen |
| 元智大學 |
2023-08-01 |
VLSI design of new sorting method implements to the ORBGRAND
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Szu-Hao Huang; Cheng-Hung Lin |
| 國立成功大學 |
2023 |
VLSI Design of Number Theoretic Transform for BGV Fully Homomorphic Encryption
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Chen, K.-Y.;Shieh, M.-D. |
| 臺大學術典藏 |
2007 |
VLSI DESIGN OF WAVELET TRANSFORM, ANALYSIS, ARCHITECTURE, AND DESIGN EXAMPLES
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Chen, Liang-Gee; Huang, Chao-Tsung; Chen, Ching-Yeh; Cheng, Chih-Chi; Chen, Liang-Gee; Huang, Chao-Tsung; Chen, Ching-Yeh; Cheng, Chih-Chi |
顯示項目 915416-915425 / 2346275 (共234628頁)
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