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Showing items 91551-91560 of 2351377 (235138 Page(s) Totally)
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| 國立臺灣大學 |
2006 |
A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology
|
Lee, Jri |
| 國立臺灣大學 |
2008 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, Mingchung |
| 國立臺灣大學 |
2008-03 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, M. |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
|
Lee, Jri;Wu, Ke-Chung; Lee, Jri; Wu, Ke-Chung; JRI LEE |
| 國立交通大學 |
2014-12-08T15:34:51Z |
A 20-Gb/s Optical Receiver with Integrated Photo Detector in 40-nm CMOS
|
Huang, Shih-Hao; Chen, Wei-Zen |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-Gb/s transmitter with adaptive preemphasis in 65-nm CMOS technology
|
Kao, S.-Y.;Liu, S.-I.; Kao, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 國立交通大學 |
2019-04-02T06:04:28Z |
A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery
|
Lee, Yuan-Sheng; Chen, Wei-Zen |
| 國立彰化師範大學 |
2005-02 |
A 20-GHz CMOS RF Down-Conversion with an On-chip Antenna
|
Su, Yu; Lin, Jau-Jr; Kenneth, K. O. |
| 臺大學術典藏 |
2018-09-10T15:00:41Z |
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator
|
Y-H Kang;C-Y Lin;T-C Lee; Y-H Kang; C-Y Lin; T-C Lee; TAI-CHENG LEE |
| 臺大學術典藏 |
2020-06-11T06:20:57Z |
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator.
|
Kang, Yu-Hsuan;Lin, Chin-Yu;Lee, Tai-Cheng; Kang, Yu-Hsuan; Lin, Chin-Yu; Lee, Tai-Cheng; TAI-CHENG LEE |
Showing items 91551-91560 of 2351377 (235138 Page(s) Totally)
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