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Institution	Date	Title	Author
國立臺灣大學	2003	VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems	Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu
國立臺灣師範大學	2019-09-03T10:49:33Z	VLSI Design of Advanced Encryption Standard	葉幸彰; Hsing-Chang Yeh
國立中山大學	2000-08	VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking	Shen-Fu Hsiao;Yor-Chin Tai;Kai-Hsiang Chang
國立中山大學	2000-06	VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking	Shen-Fu Hsiao; Yor-Chin Tai; Kai-Hsiang Chang
國立成功大學	2019-01	VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications	Shiau;Yeu-Horng;Kuo;Yao-Tsung;Chen;Pei-Yin;Hsu;Feng-Yuan
東方設計學院	2011-02	VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm	Kuan,; Ta-Wen; Wang, Jhing-Fa; Wang, Jia-Ching; Lin, Po-Chuan; Gu, Gaung-Hui; 林博川; (東方設計學院電子與資訊系)
國立成功大學	2012-04	VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm	Kuan, Ta-Wen; Wang, Jhing-Fa; Wang, Jia-Ching; Lin, Po-Chuan; Gu, Gaung-Hui
國立臺灣大學	1995-05	VLSI design of clustering analyser using systolic arrays	Lai, M.F.; Nakano, M.; Wu, Y.P.; Hsieh, C.H.
臺大學術典藏	2004-05	VLSI design of dual-mode Viterbi/turbo decoder for 3GPP	Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu
國立臺灣大學	2004-05	VLSI design of dual-mode Viterbi/turbo decoder for 3GPP	Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu
元智大學	Feb-15	VLSI Design of FM0/Manchester Encoder with Reuse-Oriented Boolean Simplification Technique for DSRC Applications	Yu-Hsuan Lee; Cheng-Wei Pan
義守大學	2001-11	VLSI Design of Inverse-Free Berlekamp-Massey Algorithm for Reed-Solomon Code	Truong, T.K. ; Chang, Y.W. ; Jeng, J.H.
元智大學	Jan-16	VLSI Design of Lossless Frame Recompression Using Multi-Orientation Prediction	Yu-Hsuan Lee; Yi-Lun You; Yi-Guo Chen
元智大學	2023-08-01	VLSI design of new sorting method implements to the ORBGRAND	Szu-Hao Huang; Cheng-Hung Lin
國立成功大學	2023	VLSI Design of Number Theoretic Transform for BGV Fully Homomorphic Encryption	Chen, K.-Y.;Shieh, M.-D.
國立成功大學	2024	VLSI Design of Programmable Bootstrapping for Torus Fully Homomorphic Encryption	Yang;T, -S.;Wu;Q, -X.;Shieh;M, -D.;Tsai;T, -H.
臺大學術典藏	2007	VLSI DESIGN OF WAVELET TRANSFORM, ANALYSIS, ARCHITECTURE, AND DESIGN EXAMPLES	Chen, Liang-Gee; Huang, Chao-Tsung; Chen, Ching-Yeh; Cheng, Chih-Chi; Chen, Liang-Gee; Huang, Chao-Tsung; Chen, Ching-Yeh; Cheng, Chih-Chi
國立臺灣大學	2007	VLSI DESIGN OF WAVELET TRANSFORM, ANALYSIS, ARCHITECTURE, AND DESIGN EXAMPLES	Chen, Liang-Gee; Huang, Chao-Tsung; Chen, Ching-Yeh; Cheng, Chih-Chi
國立交通大學	2014-12-08T15:26:27Z	VLSI implememtation for MAC-level DWT architecture	Huang, SR; Dung, LR
國立成功大學	2019	VLSI Implementation for an Adaptive Haze Removal Method	Kuo;Yao-Tsung;Chen;Wei-Ting;Chen;Pei-Yin;Li;Cheng-Hsien
國立交通大學	2014-12-08T15:36:44Z	VLSI implementation for Epileptic Seizure Prediction System based on Wavelet and Chaos Theory	Hung, Shao-Hang; Chao, Chih-Feng; Wang, Shu-Kai; Lin, Bor-Shyh; Lin, Chin-Teng
中華大學	2006	VLSI Implementation of 2-D Discrete Cosine Transform Architecture Based on CORDIC Rotation	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of 2-D Discrete Cosine Transform Architecture Based on CORDIC Rotation,	謝曜式; Shieh, Yaw-Shih
臺大學術典藏	2018-09-10T06:30:42Z	VLSI implementation of 2-D discrete wavelet transform for real-time video signal processing	Yu, C.; Chen, S.-J.; SAO-JIE CHEN
中華大學	2005	VLSI Implementation of a CORDIC-Based 2-D Discrete Cosine Transform and Its Inverse	宋志雲; Sung, Tze-Yun
中華大學	2005	VLSI Implementation of a CORDIC-Based 2-D Discrete Cosine Transform and Its Inverse	謝曜式; Shieh, Yaw-Shih
中華大學	2005	VLSI Implementation of a CORDIC-Based 2-D Discrete Cosine Transform and Its Inverse	林國珍; Lin, Kuo-Jen
中華大學	2006	VLSI Implementation of A High-Efficient and Cost-Effective LCD Signal Processor	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of a High-Efficient and Cost-Effective LCD Singal Processor,	謝曜式; Shieh, Yaw-Shih
中華大學	2006	VLSI Implementation of A High-Efficient Image Scalar Algorithm for LCD Signal Processor	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of A High-Efficient Image Scalar Algorithm for LCD Signal Processor	謝曜式; Shieh, Yaw-Shih
國立中山大學	1997-06	VLSI Implementation of a High-Throughput CORDIC Processor for Both Angle Calculation and Vector Rotation	Shen-Fu Hsiao; Jen-Yin Chen
國立交通大學	2014-12-08T15:35:45Z	VLSI Implementation of a Low Complexity 4x4 MIMO Sphere Decoder with Table Enumeration	Yang, Kai-Jiun; Tsai, Shang-Ho; Chang, Ruei-Ching; Chen, Yan-Cheng; Chuang, Gene C. -H.
中華大學	2005	VLSI Implementation of a Memory-Efficient and High-Speed Split-Radix FFT/IFF Processor for Wireless LAN	林國珍; Lin, Kuo-Jen
中華大學	2005	VLSI Implementation of a Memory-Efficient and High-Speed Split-Radix FFT/IFFT Processor for Wireless LAN	宋志雲; Sung, Tze-Yun
中華大學	2005	VLSI Implementation of a Memory-Efficient and High-Speed Split-Radix FFT/IFFT Processor for Wireless LAN	謝曜式; Shieh, Yaw-Shih
國立交通大學	2014-12-08T15:20:30Z	VLSI Implementation of a Mixed Bio-signal Lossless Data Compressor for Portable Brain-Heart Monitoring Systems	Chua, Ericson; Fu, Chih-Chung; Fang, Wai-Chi
國立成功大學	2006-12	VLSI implementation of a modified efficient SPIHT encoder	Huang, Win-Bin; Su, Alvin W. Y.; Kuo, Yau-Hwang
臺大學術典藏	2018-09-10T05:50:34Z	Vlsi implementation of a selective median filter	Chen, C.-T.; Chen, L.-G.; Hsiao, J.-H.; LIANG-GEE CHEN
國立成功大學	2009-09	VLSI Implementation of an Edge-Oriented Image Scaling Processor	Chen, Pei-Yin; Lien, Chih-Yuan; Lu, Chi-Pin
國立交通大學	2014-12-08T15:04:18Z	VLSI IMPLEMENTATION OF AN M-ARRAY IMAGE FILTER BASED ON SHIFT REGISTER ARRAY	LEE, CY; TSAI, JM; HSU, SC
中國文化大學	2018-04	VLSI implementation of an ultra-low-cost and low-power image compressor for wireless camera networks	Chen, SL (Chen, Shih-Lun); Nie, J (Nie, Jing); Lin, TL (Lin, Ting-Lan); Chung, RL (Chung, Rih-Lung); Hsia, CH (Hsia, Chih-Hsien); Liu, TY (Liu, Tse-Yen); Lin, SY (Lin, Szu-Yin); Wu, HX (Wu, Hai-Xia)
中華大學	2006	VLSI Implementation of CORDIC-Based Geometry Rotation for High-Speed 3-D Computer Graphic Systems	宋志雲; Sung, Tze-Yun
國立中山大學	1997-06	VLSI Implementation of Digit-On-Line CORDIC with Constant Scaling Factor	Shen-Fu Hsiao; Jen-Yin Chen
中華大學	2008	VLSI Implementation of Discrete Wavelet Transform with Lifting Scheme	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of Double- Rotation CORDIC Arithmetic	謝曜式; Shieh, Yaw-Shih
中華大學	2006	VLSI Implementation of Double- Rotation CORDIC Arithmetic (DRCA)	宋志雲; Sung, Tze-Yun
國立中山大學	1994-12	VLSI Implementation of Fully Pipelined Hadamard Transform	Shen-Fu Hsiao; Vincent Tsai
中華大學	2006	VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors	謝曜式; Shieh, Yaw-Shih

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