臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
中華大學	2006	VLSI Implementation of Double- Rotation CORDIC Arithmetic	謝曜式; Shieh, Yaw-Shih
中華大學	2006	VLSI Implementation of Double- Rotation CORDIC Arithmetic (DRCA)	宋志雲; Sung, Tze-Yun
國立中山大學	1994-12	VLSI Implementation of Fully Pipelined Hadamard Transform	Shen-Fu Hsiao; Vincent Tsai
中華大學	2006	VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of High-Efficient 2-D Lifting-Based DWT and IDWT Processors	謝曜式; Shieh, Yaw-Shih
國立聯合大學	2007	VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems	Tze-Yun Sung, Hsi-Chin Hsin
中華大學	2007	VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems	宋志雲; Sung, Tze-Yun
國立成功大學	2004-06	VLSI implementation of implantable wireless power and data transmission micro-stimulator for neuromuscular stimulation	Lee, Shuenn-Yuh; Lev, Shyh-Chyang; Chen, Jia-Jin Jason
中華大學	2013	VLSI IMPLEMENTATION OF LOW-POWER AND HIGH-SFDR DIGITAL FREQUENCY SYNTHESIZER FOR UNDERWATER INSTRUMENTS AND NETWORK SYSTEMS	莊英慎; Juang, Ying-Shen
中華大學	2013	VLSI IMPLEMENTATION OF LOW-POWER AND HIGH-SFDR DIGITAL FREQUENCY SYNTHESIZER FOR UNDERWATER INSTRUMENTS AND NETWORK SYSTEMS	宋志雲; Sung, Tze-Yun
國立高雄第一科技大學	2006.04	VLSI implementation of low-power high-quality color interpolation processor for CCD camera	Hsia, Shih-Chang;Chen, Ming-Huei;Tsai, Po-Shien
中華大學	2006	VLSI Implementation of Memory-Efficiency Multiplierless DCT and IDCT Processors	宋志雲; Sung, Tze-Yun
中華大學	2006	VLSI Implementation of Memory-Efficiency Multiplierless DCT and IDCT Processors	謝曜式; Shieh, Yaw-Shih
國立中山大學	1995-12	VLSI implementation of multi-valued exponential bidirectional associative memory using current-mode circuits	C.C. Wang;Y.C. Chen
中華大學	2005	VLSI Implementation of Pipelined Architectures for 2-D Discrete Wavelet Transform and Its Inversion	宋志雲; Sung, Tze-Yun
中華大學	2005	VLSI Implementation of Pipelined Architectures for 2-D Discrete Wavelet Transform and Its Inversion	謝曜式; Shieh, Yaw-Shih
中華大學	2005	VLSI Implementation of Pipelined Architectures for 2-D Discrete Wavelet Transform and Its Inversion	林國珍; Lin, Kuo-Jen
臺大學術典藏	2018-09-10T09:48:39Z	VLSI implementation of real-time motion compensated beamforming in synthetic transmit aperture imaging	Ho, K.-Y.;Chen, Y.-H.;Zhan, C.-Z.;y Wu, A.-Y.; Ho, K.-Y.; Chen, Y.-H.; Zhan, C.-Z.; y Wu, A.-Y.; AN-YEU(ANDY) WU
臺大學術典藏	2018-09-10T04:07:51Z	VLSI implementation of shape-adaptive discrete wavelet transform	Tseng, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN
臺大學術典藏	2018-09-10T06:54:39Z	VLSI implementation of the motion estimator with two-dimensional data-reuse	Lai, Y.-K.; Lai, Y.-L.; Liu, Y.-C.; Chen, L.-G.; LIANG-GEE CHEN
國立中山大學	1998-02	VLSI Implementation of the Quadratic-Spline W-Transform for Multi-resolution Image Processing	Shen-Fu Hsiao
國立聯合大學	2004	VLSI Implementation of the Universal 2-D CAT/ICAT System (EI)	陳榮堅, 賴瑞麟
國立臺灣大學	1999-06	VLSI Implementation of Timing Recovery and Carrier Recovery for QAM/VSB Dual Mode	Shyh-Jye; Kua, G. H.; Shiue, Muh-Tian; Heh, Jung-Yu; 汪重光; Shyh-Jye; Kua, G. H.; Shiue, Muh-Tian; Heh, Jung-Yu; Wang, C. K.
臺大學術典藏	2018-09-10T06:54:39Z	VLSI implementation of visual block pattern truncation coding	Liu, Y.-C.; Lai, Y.-K.; Tsai, T.-H.; Wu, P.-C.; Chen, L.-G.; LIANG-GEE CHEN
國立中山大學	1994-08	VLSI Implementations of an Error-Correcting Encoder/Decoder	Shen-Fu Hsiao

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