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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Institution Date Title Author
臺大學術典藏 2020-04-08T02:10:17Z A 59-year-old male with right lateral knee pain Wei K.-C.; Wei K.-C.;Tyng-Guey Wang; TYNG-GUEY WANG
臺大學術典藏 2018-09-10T08:08:01Z A 59.5mW scalable/multi-view video decoder chip for quad/3D full HDTV and video streaming applications Chuang, T.-D.;Tsung, P.-K.;Lin, P.-C.;Chang, L.-M.;Ma, T.-C.;Chen, Y.-H.;Chen, L.-G.; Chuang, T.-D.; Tsung, P.-K.; Lin, P.-C.; Chang, L.-M.; Ma, T.-C.; Chen, Y.-H.; Chen, L.-G.; LIANG-GEE CHEN
臺大學術典藏 2019-12-20T01:18:33Z A 5d/3d duality from relativistic integrable system Chen, H.-Y.; Hollowood, T.J.; Zhao, P.; Chen, H.-Y.; Hollowood, T.J.; Zhao, P.; HENG-YU CHEN
國立臺北護理健康大學 2021-05 A 5G Spectrum Demanding Estimation Framework Considering Coalition Formation of Taiwan Telecommunication Operator Tsai, Wang-You; Chou, Tzu-Chuan; Chen, Yen-Hung; Jan, Pi-Tzong
國立交通大學 2017-04-21T06:49:54Z A 5Gb/s Pulse Signaling Interface for Low Power On-Chip Data Communication Lin, Hung-Wen; Ho, Ying-Chieh; Fa, YingLin; Su, ChauChin
臺大學術典藏 2018-09-10T05:27:04Z A 5Gbps CMOS automatic gain control amplifier for 10GBase-LX I-Hsin Wang; Wei-Sheng Chen; Shen-Iuan Liu; SHEN-IUAN LIU
國立交通大學 2014-12-12T02:30:38Z A 5GHz CMOS Power Amplifier for IEEE 802.11a Wireless LAN 王自強; Dz-Chung Wang; 溫懷岸; 羅正忠; Kuei-Ann Wen; Jen-Chung Lou
國立臺灣大學 2004 A 5GHz LNA with new compact gain controllable active balun for ISM band applications Rajashekharaiah, Mallesh; Upadhyaya, Parag; Heo, Deukhyoun; Chen, Yi-Jan Emery
國立臺灣科技大學 2007 A 5GHz low phase noise hartley quadrature CMOS VCO Jang S.-L.; Chen H.-M.; Han J.-C.; Lee C.-F.; Jhuang Y.-D.
臺大學術典藏 2018-09-10T07:43:10Z A 5GHz Phase-Locked Loop Using Dynamic Phase-Error Compensation Technique for Fast Settling in 0.18-μm CMOS W.-H. Chiu;Y.-H. Huang;T.-H. Lin; W.-H. Chiu; Y.-H. Huang; T.-H. Lin; TSUNG-HSIEN LIN
臺大學術典藏 2018-09-10T05:50:33Z A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications Lin, C.-P.; Tseng, P.-C.; Chiu, Y.-T.; Lin, S.-S.; Cheng, C.-C.; Fang, H.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN
亞洲大學 2010-11 A 5V/200V SOI Device with a Vertically Linear Graded Drift Region 楊紹明;Yang, Shao-Ming;許健;Sheu, Gene;蔡宗叡;Tsai, Jung-Ruey
國立臺灣大學 2007 A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler Chen, Hsiao-Chin; Wang, Tao; Lu, Shey-Shi
國立臺灣科技大學 2007 A 6 GHz low power differential VCO Jang, S.-L.;Lee, S.-H.;Chiu, C.-C.;Chuang, Y.-H.
臺大學術典藏 2002-05 A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei
國立臺灣大學 2002-05 A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan
國立交通大學 2014-12-08T15:25:24Z A 6 similar to 10-GHz ultra-WideBand tunable LNA Chen, YC; Kuo, CN
臺大學術典藏 2018-09-10T14:57:27Z A 6-Bit 1 GS/s pipeline ADC using incomplete settling with background sampling-point calibration Lai, C.-F.; Chen, H.-S.; HSIN-SHU CHEN; Tseng, C.-J.;Lai, C.-F.;Chen, H.-S.; Tseng, C.-J.
臺大學術典藏 2018-09-10T14:57:27Z A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS Tai, H.-Y.;Tsai, C.-H.;Tsai, P.-Y.;Chen, H.-W.;Chen, H.-S.; Tai, H.-Y.; Tsai, C.-H.; Tsai, P.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN
國立臺灣科技大學 2018 A 6-bit 1.3-GS/s ping-pong domino-SAR ADC in 55-nm CMOS Chung Y.-H.; Rih W.-S.; Chang C.-W.
國立臺灣科技大學 2018 A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS Chung, Y.-H.;Rih, W.-S.
臺大學術典藏 2004-08 A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter Chen, Yu-Hsun; Lee, Tai-Cheng; Chen, Yu-Hsun; Lee, Tai-Cheng
國立臺灣大學 2004-08 A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter Chen, Yu-Hsun; Lee, Tai-Cheng
國立臺灣大學 2007 A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers Shen, Ding-Lan; Lee, Tai-Cheng
國立成功大學 2012-11 A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications Chen, Ren-Li; Chang, Soon-Jyh

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