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顯示項目 92261-92270 / 2348439 (共234844頁)
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| 國立臺灣大學 |
2007 |
A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler
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Chen, Hsiao-Chin; Wang, Tao; Lu, Shey-Shi |
| 國立臺灣科技大學 |
2007 |
A 6 GHz low power differential VCO
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Jang, S.-L.;Lee, S.-H.;Chiu, C.-C.;Chuang, Y.-H. |
| 臺大學術典藏 |
2002-05 |
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
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Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan; Chang, Hsiang-Hui; Lin, Jyh-Woei |
| 國立臺灣大學 |
2002-05 |
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
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Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan |
| 國立交通大學 |
2014-12-08T15:25:24Z |
A 6 similar to 10-GHz ultra-WideBand tunable LNA
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Chen, YC; Kuo, CN |
| 臺大學術典藏 |
2018-09-10T14:57:27Z |
A 6-Bit 1 GS/s pipeline ADC using incomplete settling with background sampling-point calibration
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Lai, C.-F.; Chen, H.-S.; HSIN-SHU CHEN; Tseng, C.-J.;Lai, C.-F.;Chen, H.-S.; Tseng, C.-J. |
| 臺大學術典藏 |
2018-09-10T14:57:27Z |
A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS
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Tai, H.-Y.;Tsai, C.-H.;Tsai, P.-Y.;Chen, H.-W.;Chen, H.-S.; Tai, H.-Y.; Tsai, C.-H.; Tsai, P.-Y.; Chen, H.-W.; Chen, H.-S.; HSIN-SHU CHEN |
| 國立臺灣科技大學 |
2018 |
A 6-bit 1.3-GS/s ping-pong domino-SAR ADC in 55-nm CMOS
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Chung Y.-H.; Rih W.-S.; Chang C.-W. |
| 國立臺灣科技大學 |
2018 |
A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS
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Chung, Y.-H.;Rih, W.-S. |
| 臺大學術典藏 |
2004-08 |
A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter
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Chen, Yu-Hsun; Lee, Tai-Cheng; Chen, Yu-Hsun; Lee, Tai-Cheng |
顯示項目 92261-92270 / 2348439 (共234844頁)
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